M7040N datasheet(64/159 Pages) STMICROELECTRONICS

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M7040N

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Table 32. Latency of SEARCH from Instruction to SRAM Access Cycle

Table 33. Shift of SSF and SSV from SADR

144-bit Configuration with Single Device

The hardware diagram for this search subsystem

is shown in Figure 44.

Figure 45, page 66 shows the timing diagram for a

SEARCH command in the 144-bit-configured ta-

ble (CFG = 0101010101010101) consisting of a

single device for one set of parameters. This illus-

tration assumes that the host ASIC has pro-

grammed TLSZ to '00,' HLAT to '001,' LRAM to '1,'

and LDEV to '1.'

The following is the operation sequence for a sin-

gle 144-bit SEARCH command (refer to COM-

MAND CODES AND PARAMETERS, page 30).

– Cycle A: The host ASIC drives the CMDV high

and applies SEARCH command code ('10') to

CMD[1:0] signals. {CMD[10],CMD[5:3]} signals

must be driven with the index to the GMR pair

for use in this SEARCH operation. CMD[8:6]

signals must be driven with the same bits that

will be driven on SADR[23:21] by this device if it

has a hit. DQ[71:0] must be driven with the 72-

bit data ([143:72]) to be compared against all

even locations. The CMD[2] signal must be driv-

en to logic '0.'

– Cycle B: The host ASIC continues to drive the

CMDV high and applies the command code of

command

('10')

CMD[1:0].

CMD[5:2] must be driven by the index of the

comparand register pair for storing the 144-bit

word presented on the DQ Bus during Cycles A

and B. CMD[8:6] signals must be driven with the

index of the SSR that will be used for storing the

address of the matching entry and Hit Flag (see

SEARCH-Successful

Registers

(SSR[0:7]),

page 24). The DQ[71:0] is driven with 72-bit

data ([71:0]), compared to all odd locations.

Note: For 144-bit searches, the host ASIC must

supply two distinct 72-bit data words on

DQ[71:0] during Cycles A and B. The even-

numbered GMR of the pair specified by the

GMR Index is used for masking the word in Cy-

cle A. The odd-numbered GMR of the pair spec-

ified by the GMR Index is used for masking the

word in Cycle B.

# of devices

Max Table Size

Latency in CLK Cycles

1 (TLSZ = 00)

64K x 72-bit

1–8 (TLSZ = 01)

512K x 72-bit

1–31 (TLSZ = 10)

1984K x 72-bit

HLAT

Number of CLK Cycles

000

001

010

011

100

101

110

111

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