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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M7040N датащи(PDF) 18 Page - STMicroelectronics |
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M7040N датащи(HTML) 18 Page - STMicroelectronics |
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18 / 159 page  M7040N 18/159 Table 8. AC Timing Parameters with CLK1X Note: 1. Valid for Ambient Operating Temperature: TA =0to70°C; VDD =1.5V. 2. Values are based on 50% signal levels and a 50/50% duty cycle of CLK1X. 3. Based on an AC load of CL = 30pF (see Figure 5, Figure 6, and Figure 7, page 13). 4. These parameters are sampled and not 100% tested, and are based on an AC load of 5pF. Row Sym M7040N- 066 M7040N- 083 M7040N- 100 Unit Description(1) (VDDQ = 3.3V, 2.5V, 1.8V) (VDDQ = 3.3V, 2.5V, 1.8V) (VDDQ = 3.3V, 2.5V) Min Max Min Max Min Max 1 fCLOCK 20 66 20 83 20 100 MHz CLK1X frequency 2 tCLOK 0.5 0.5 0.5 ms PLL lock time 3 tCKHI 6.75 5.4 4.5 ns CLK1X high pulse(2) 4 tCKLO 6.75 5.4 4.5 ns CLK1X low pulse(2) 5 tISCH 2.5 1.8 1.5 ns Input Setup Time to CLK1X edge(2) 6 tIHCH 0.6 0.6 0.5 ns Input Hold Time to CLK1X edge(2) 7 tICSCH 4.2 3.5 3.0 ns Cascaded Input Setup Time to CLK1X rising edge(2) 8 tICHCH 0.6 0.5 0.5 ns Cascaded Input Hold Time to CLK1X rising edge(2) 9 tCKHOV 8.5 7.0 6.5 ns Rising edge of CLK1X to LHO, FULO, BHO, FULL valid(3) 10 tCKHDV 9.0 7.5 7.0 ns Rising edge of CLK1X to DQ valid(3) 11 tCKHDZ 8.5 7.0 6.5 ns Rising edge of CLK1X to DQ high-Z(4) 12 tCKHSV 9.0 7.5 7.0 ns Rising edge of CLK1X to SRAM bus valid(3) 13 tCKHSHZ 6.5 6.0 5.5 ns Rising edge of CLK1X to SRAM bus high-Z(4) 14 tCKHSLZ 7.0 6.5 6.0 ns Rising edge of CLK1X to SRAM bus low-Z(4) |
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