AT25DF021A-DWFHT datasheet(22/59 Pages) RENESAS

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DS-AT25DF021A-042 Rev. L

Page 22

8/7/23

AT25DF021A Datasheet

8.6

Chip Erase

The entire memory array can be erased in a single operation by using the Chip Erase command. Before a Chip

Erase command can be started, the Write Enable command must have been previously issued to the device to set

the WEL bit of the Status Register to a logical 1 state.

Two opcodes (60h and C7h) can be used for the Chip Erase command. There is no difference in device

functionality when utilizing the two opcodes, so they can be used interchangeably. To perform a Chip Erase, one

of the two opcodes must be clocked into the device. Since the entire memory array is to be erased, no address

bytes are required to be clocked into the device, and any data clocked in after the opcode is ignored. When the CS

pin is deasserted, the device erases the entire memory array. The erasing of the device is internally self-timed and

takes place in a time of tCHPE.

The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be

deasserted on an even byte boundary (multiples of eight bits); otherwise, no erase is performed. Also, if any

sector in the memory array is in the protected state, then the Chip Erase command is not executed, and the

device returns to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register is reset

back to the logical 0 state if the CS pin is deasserted on uneven byte boundaries or if the memory is in the

protected state.

While the device is executing a successful erase cycle, the Status Register can be read and indicates that the

device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the

tCHPE time to determine if the device has finished erasing. At some point before the erase cycle completes, the

WEL bit in the Status Register is reset back to the logical 0 state.

The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase

properly. If an erase error occurs, it is indicated by the EPE bit in the Status Register.

Figure 18. Chip Erase

SCK

MSB

CCCCCCCC

OPCODE

High-Impedance

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