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AT25DF021A-DWFHT датащи(PDF) 30 Page - Renesas Technology Corp

номер детали AT25DF021A-DWFHT
подробное описание детали  2-Mbit, 1.65 V Minimum SPI Serial Flash Memory with Dual-I/O Support
PDF  59 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

AT25DF021A-DWFHT датащи(HTML) 30 Page - Renesas Technology Corp

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DS-AT25DF021A-042 Rev. L
Page 30
8/7/23
© 2023 Renesas Electronics
AT25DF021A Datasheet
deasserted on uneven byte boundaries, or because the user-programmable portion of the OTP Security Register
was previously programmed.
While the device is programming the OTP Security Register, the Status Register can be read and indicates that
the device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting
the tOTPP time to determine if the data bytes have finished programming. At some point before the OTP Security
Register programming completes, the WEL bit in the Status Register is reset back to the logical 0 state.
If the device is powered-down during the OTP Security Register program cycle, then the contents of the 64-byte
user programmable portion of the OTP Security Register cannot be guaranteed and cannot be programmed
again.
The Program OTP Security Register command uses the internal 256-buffer for processing. Thus, the contents of
the buffer is altered from its previous state when this command is issued.
Figure 24. Program OTP Security Register
10.2 Read OTP Security Register
The OTP Security Register can be sequentially read in a similar fashion to the Read Array operation up to the
maximum clock frequency specified by fCLK. To read the OTP Security Register, the CS pin must first be asserted
and the opcode of 77h must be clocked into the device. After the opcode has been clocked in, the three address
bytes must be clocked in to specify the starting address location of the first byte to read within the OTP Security
Register. Following the three address bytes, two dummy bytes must be clocked into the device before data can be
output.
After the three address bytes and the dummy bytes have been clocked in, additional clock cycles result in OTP
Security Register data being output on the SO pin. When the last byte (03FFFFh) of the OTP Security Register
has been read, the device continues reading back at the beginning of the register (000000h). No delays are
incurred when wrapping around from the end of the register to the beginning of the register.
Deasserting the CS pin stops the read operation and put the SO pin into a high-impedance state. The CS pin can
be deasserted at any time and does not require that a full byte of data be read.
Figure 25. Read OTP Security Register
SCK
CS
SI
SO
MSB
MSB
23
1
0
10011011
67
5
49
839
37 38
33
36
35
34
31 32
29 30
OPCODE
High-Impedance
AA
AAA
A
MSB
DDDDDDDD
ADDRESS BITS A23-A0
DATA IN BYTE 1
MSB
DDDDDDDD
DATA IN BYTE n
SCK
CS
SI
SO
MSB
MSB
23
1
0
01110111
67
5
410 11
9
812
33
36
35
34
31 32
29 30
OPCODE
AAAA
AAA
AA
XXX
MSB
MSB
DDDDDDDD
D
D
ADDRESS BITS A23-A0
MSB
XXXXXX
DON'T CARE
DATA BYTE 1
High-Impedance



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