AT25DF021A-DWFHT datasheet(18/59 Pages) RENESAS

18 / 59 page

DS-AT25DF021A-042 Rev. L

Page 18

8/7/23

AT25DF021A Datasheet

programmed at address 000000h. The remaining bytes in the page (addresses 000001h through 0000FDh) are

not programmed and remain in the erased state (FFh).

When the CS pin is deasserted, the device programs the data stored in the internal buffer into the appropriate

memory array locations based on the starting address specified by A23-A0 and the number of data bytes sent to

the device. If fewer than 256 bytes of data is sent to the device, then the remaining bytes within the page are not

programmed and remain in the erased state (FFh). The programming of the data bytes is internally self-timed and

takes place in a time of tPP or tBP if only programming a page (tPP) or a single byte (tBP).

The three address bytes and at least one complete byte of data must be clocked into the device before the CS pin

is deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the

device stops the operation and no data are programmed into the memory array. Also, if the address specified by

A23-A0 points to a memory location within a sector that is in the protected state (see “Protect Sector” on page 24),

then the Byte/Page Program command is not executed and the device returns to the idle state once the CS pin

has been deasserted. The WEL bit in the Status Register is reset back to the Logical 0 state if the program cycle

stops due to an incomplete address being sent, an incomplete byte of data being sent, the CS pin being

deasserted on uneven byte boundaries, or because the memory location to be programmed is protected or locked

down.

While the device is programming, the Status Register can be read and indicates that the device is busy. For faster

throughput, it is recommended that the Status Register be polled rather than waiting the tBP or tPP time to

determine if the data bytes have finished programming. For fastest throughput and least power consumption, it is

recommended that the Active Status Interrupt command 25h be used. At some point before the program cycle

completes, the WEL bit in the Status Register is reset back to the Logical 0 state.

The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to

program properly. If a programming error arises, it is indicated by the EPE bit in the Status Register.

Figure 13. Dual-Input Byte Program

Figure 14. Dual-Input Page Program

SCK

SI (SIO)

SO (SOI)

MSB

10100010

410 11

812

31 32

29 30

Opcode

AAAA

AAA

Address Bits A23-A0

MSB

Input

Data Byte

High-Impedance

SCK

SI (SIO)

SO (SOI)

MSB

10100010

410 11

812

37 38

31 32

29 30

Opcode

AAAA

AAA

MSB

Address Bits A23-A0

Input

Data Byte 1

MSB

Input

Data Byte n

Input

Data Byte 2

High-Impedance

AT25DF021A-DWFHT датащи(PDF) 18 Page - Renesas Technology Corp

AT25DF021A-DWFHT датащи(HTML) 18 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

датащи скачать

ссылки URL