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AT25DF021A-DWFHT датащи(PDF) 33 Page - Renesas Technology Corp |
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AT25DF021A-DWFHT датащи(HTML) 33 Page - Renesas Technology Corp |
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33 / 59 page ![]() DS-AT25DF021A-042 Rev. L Page 33 8/7/23 © 2023 Renesas Electronics AT25DF021A Datasheet reset when an operation stops prematurely, the entire opcode for a program, erase, Protect Sector, Unprotect Sector, or Write Status Register command must have been clocked into the device. 11.1.7 RDY/BSY Bit The RDY/BSY bit is used to determine whether or not an internal operation, such as a program or erase, is in progress. To poll the RDY/BSY bit to detect the completion of a program or erase cycle, new Status Register data must be continually clocked out of the device until the state of the RDY/BSY bit changes from a logical 1 to a logical 0.Note that the RDY/BSY bit can be read either from Status Register Byte 1 or from Status Register Byte 2. See also the Active Status Interrupt command. (11.2) Figure 26. Read Status Register 11.1.8 RSTE Bit The RSTE bit is used to enable or disable the Reset command. When the RSTE bit is in the Logical 0 state (the default state after power-up), the Reset command is disabled and any attempts to reset the device using the Reset command is ignored. When the RSTE bit is in the Logical 1 state, the Reset command is enabled. The RSTE bit retains its state as long as power is applied to the device. Once set to the Logical 1 state, the RSTE bit remains in that state until it is modified using the Write Status Register Byte 2 command or until the device has been power cycled. The Reset command itself does not change the state of the RSTE bit. Table 10. Status Register Format – Byte 2 Bit[1] 1. Only bit 4 of Status Register Byte 2 is modified when using the Write Status Register Byte 2 command Name Type[2]) 2. R/W = Readable and Writeable, R = Readable only. Description 7 RES Reserved for future use R 0 Reserved for future use 6 RES Reserved for future use R 0 Reserved for future use 5 RES Reserved for future use R 0 Reserved for future use 4 RSTE Reset Enabled R/W 0 Reset command is disabled (default) 1 Reset command is enabled 3 RES Reserved for future use R 0 Reserved for future use 2 RES Reserved for future use R 0 Reserved for future use 1 RES Reserved for future use R 0 Reserved for future use 0 RDY/BSY Ready/Busy Status R 0 Device is ready 1 Device is busy with an internal operation SCK CS SI SO MSB 23 1 0 00000101 67 5 410 11 9 812 21 22 17 20 19 18 15 16 13 14 23 24 OPCODE MSB MSB DDDDDD DD D D MSB DDDDDD D D STATUS REGISTER BYTE1 STATUS REGISTER BYTE2 HIGH-IMPEDANCE |
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