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L9805 датащи(PDF) 51 Page - STMicroelectronics |
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L9805 датащи(HTML) 51 Page - STMicroelectronics |
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51 / 103 page ![]() 51/103 L9805 5.3.3 Register Description The PWM is associated with a 8-bit control regis- ters, and with two 16-bit data registers, each split in two 8-bit registers. PWM CYCLE REGISTER LOW (CYREGL) PWM1 Register Address: 0011h PWM2 Register Address: 0019h Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be multiplied by internal clock period. PWM CYCLE REGISTER HIGH (CYREGH) PWM1 Register Address: 0010h PWM2 Register Address: 0018h Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the high part of the value to be multiplied by internal clock peri- od. PWM DUTYCYCLE REGISTER LOW (DU- TYREGL) PWM1 Register Address: 0013h PWM2 Register Address: 001Bh Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value corresponding to the binary weight of the PWM pulse. PWM DUTYCYCLE REGISTER HIGH (DU- TYREGH) PWM1 Register Address: 0012h PWM2 Register Address: 001Ah Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the high part of the value corresponding to the binary weight of the PWM pulse . PWM CONTROL REGISTER (CONREG) PWM1 Register Address: 0014h PWM2 Register Address: 001Ch Read/Write Reset Value: 0000 0000 (00h) Bit 0= EN _PWM: 1 = enables the PWM output, 0 = disables PWM output. Bit 1= EN _INT: 1 = enables interrupt request, 0 disables interrupt request. Bit 4, 3, 2= PS2,PS1,PS0: prescaler bits The value of the PWM internal clock depends on these bits. Bit 5, 6, 7= not used. 70 MSB LSB 70 MSB LSB 70 MSB LSB 70 MSB LSB 7 4 32 10 0 0 0 PS2 PS1 PS0 EN_ INT EN_ PWM PS2 PS1 PS0 PWM internal clock 00 0 fCPU 00 1 fCPU / 2 01 0 fCPU / 4 01 1 fCPU / 8 10 0 fCPU / 16 10 1 fCPU / 32 11 0 fCPU / 64 11 1 fCPU / 128 |
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