L9805 datasheet(41/103 Pages) STMICROELECTRONICS

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L9805

16-BIT TIMER (Cont’d)

5.2.3.7 Pulse Width Modulation Mode

Pulse Width Modulation mode enables the gener-

ation of a signal with a frequency and pulse length

determined by the value of the OCR1 and OCR2

registers.

The pulse width modulation mode uses the com-

plete Output Compare 1 function plus the OCR2

Procedure

To use pulse width modulation mode select the fol-

lowing in the CR1 register:

– Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after a successful com-

parison with OCR1 register.

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin after a successful com-

parison with OCR2 register.

– Set OC1E bit: the OCMP1 pin is then dedicated

to the output compare 1 function.

And select the following in the CR2 register:

– Set the PWM bit.

– Select the timer clock (CC1-CC0) (see Table 7

Clock Control Bits).

Load the OCR2 register with the value corre-

sponding to the period of the signal.

Load the OCR1 register with the value corre-

sponding to the length of the pulse if (OLVL1=0

and OLVL2=1).

If OLVL1=1 and OLVL2=0 the length of the pulse

is the difference between the OCR2 and OCR1

registers.

The OCRi register value required for a specific tim-

ing application can be calculated using the follow-

ing formula:

Where:

– t = Desired output compare period (seconds)

–fCPU = Internal clock frequency (see Miscella-

neous register)

– CC1-CC0 = Timer clock prescaler

The Output Compare 2 event causes the counter

to be initialized to FFFCh (See Figure 25, on

page 42).

Note: After a write instruction to the OCHRi regis-

ter, the output compare function is inhibited until

the OCLRi register is also written.

The OCF1 and OCF2 bits cannot be set by hard-

ware in PWM mode therefore the Output Compare

interrupt is inhibited. The Input Capture interrupt is

available.

When the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

OCRi Value =

t * fCPU

(CC1.CC0)

- 5

Counter

Counter is reset

to FFFCh

OCMP1 = OLVL2

Counter

= OCR2

OCMP1 = OLVL1

When

= OCR1

Pulse Width Modulation cycle

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