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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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L9805 датащи(PDF) 64 Page - STMicroelectronics |
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L9805 датащи(HTML) 64 Page - STMicroelectronics |
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64 / 103 page  64/103 L9805 – ERROR. The error management as described in the CAN protocol is completely handled by hard- ware using 2 error counters which get increment- ed or decremented according to the error condition. Both of them may be read by the appli- cation to determine the stability of the network. Moreover, as one of the node status bits (EPSV or BOFF of the CSR register) changes, an inter- rupt is generated if the SCIE bit is set in the ICR Register. Refer to Figure 37. Figure 37. CAN Error State Diagram ERROR PASSIVE When TECR or RECR > 127, the EPSV bit gets set When TECR and RECR < 128, and the EPSV bit gets cleared ERROR ACTIVE BUS OFF When TECR > 255 the BOFF bit gets set When 128 * 11 recessive bits occur: - the BOFF bit gets cleared - the TECR register gets cleared - the RECR register gets cleared the EPSV bit gets cleared |
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