L9805 datasheet(77/103 Pages) STMICROELECTRONICS

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L9805

5.8 POWER BRIDGE

5.8.1 Introduction

The power part of the device consists of two iden-

tical independent DMOS half bridges. It is suited to

drive resistive and inductive loads.

5.8.2 Main Features

The Rdson of each of the 4 DMOS transistors is 60

Ω at 25°C.

The nominal current is 2A.

The maximum current is 5A.

The low-side switch is a n-channel DMOS transis-

tor while the high-side switch is a p-channel

DMOS transistor. Therefore no charge pump is

needed.

An anti-crossconduction circuit is included: the low

side DMOS is switched on only when the high side

is switched off and vice versa. This function avoid

the two DMOS are switched on together firing the

high current path from battery to ground. The func-

tion is obtained by sensing the gate voltage and

therefore the delay between command and effec-

tive switch on of the DMOS doesn’t have a fixed

length.

The MCU controls all operations of the power

stage through the BCSR dedicated register. Short

circuit and overtemperature conditions are report-

ed to the CPU using dedicated error flags.

Overtemperature and short circuit conditions

switch off the bridge immediately without CPU in-

tervention. The function of the flags is independent

of the operation mode of the bridge (sink, source,

Z).

In addition both the PWM modules can be directly

connected to the power bridge. The power bridge

offers then many driving mode alternatives:

Direct Mode: the two half bridges are directly driv-

en by IN1 and IN2 control bit in BCSR.

PWM1 Up/Down Brake Mode: the output of PWM1

drives one side of the bridge while the other side is

maintained in a fixed status.

PWM1 Symmetrical Driving Mode: PWM1 line

drives directly and symmetrically both side of the

bridge.

PWM1/PWM2 Mode: PWM1 drives one side while

PWM2 drives the other (two independent half

bridges).

5.8.3 Functional Description

A schematic description of the Power Bridge cir-

cuit is depicted in Figure 41. In this schematic the

transistors must be considered in ON condition

when they gate is high (set).

Figure 41. Power Bridge Schematic

EN bit in BCSR is the main enable signal, active

high. If EN = 0, all the bridge transistors are

switched off (UL, UR, DL and DR are reset) and

the outputs OUTL and OUTR are in high imped-

ance state.

Being '0' the status after reset of EN, the bridge is

in safe condition (OUTL=OUTR=Z). Therefore the

VBR

PGND

OUTR

VBL

PGND

OUTL

SC_UL

OVT

SC_DL

OVT

SC_DR

OVT

SC_UR

OVT

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