L9805 datasheet(78/103 Pages) STMICROELECTRONICS

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L9805

safe condition is guaranteed in undervoltage con-

dition (LVD reset) and in case of main clock (Safe-

guard reset) or software (Watchdog reset) failures.

Each power DMOS has its own over current detec-

tor circuit generating SC_xx signals (see Figure

41). SC_xx signals are ORed together to generate

SC flag in BCSR register.

SC flag is then set by hardware as soon as one of

the two outputs (or both) are short to battery,

ground or if the two outputs are short together

(load short). This read only bit is reset only by

clearing the EN bit. The rising edge of SC causes

an interrupt request if the PIE bit is set in BCSR

When the current monitored in any of the four

DMOS of the bridge exceeds limit threshold (ISC),

the SC bit is set and the corresponding DMOS is

switched off after tSCPI time. This function is domi-

nant over any write from data bus by software (i. e.

as long as SC is set, the bridge cannot be

switched on).

To switch the bridge on again the EN bit must be

cleared by software. This resets the SC bit. Setting

again EN, the bridge is switched on. If the overcur-

rent condition is still present, SC is set again (and

a interrupt is generated when enabled).

An internal thermal protection circuit monitors con-

tinuously the temperature of the device and drives

the OVT bit in BCSR register and, in turn, the OVT

signal in Figure 41.

The OVT flag is set as soon as the temperature of

the chip exceeds Thw and all the transistor of the

bridge are switched off. This rising edge causes an

interrupt request if the PIE bit is set. This read only

bit is reset only by clearing the EN bit. This func-

tion is dominant over any write from data bus by

software (i. e. as long as OVT is set the bridge

cannot be switched on).

To switch the bridge on again the EN bit must be

cleared by software. This resets the OVT bit. Set-

ting again EN, the bridge is switched on. If the

overtemperature condition is still present, OVT is

set again (and a interrupt is generated when ena-

bled).

5.8.4 Interrupt generation

Interrupt generation is controlled by PDIE bit in

BCSR register. When this bit is set Overtempera-

ture and Short-circuit conditions generate an inter-

rupt as described in Section 5.8.3.

Setting PDIE when SC and/or OVT flag are set,

immediately generates an interrupt request.

The interrupt request of the power bridge is

cleared when the EN bit is cleared by software.

5.8.5 Operating Modes

The status of the OUTL and OUTR power outputs

is controlled by IN1, IN2, EN, PWM_EN and DIR

bit in BCSR register, plus the PWM1 and PWM2

line, according to the Functional Description Table

(Table 12).

Note The functional description table (Table 12)

uses symbols UL,R (Up Left or Right) and DR,L

(Down Left or Right) to indicate the driving signal

of the four DMOS. Conventionally a transistor is in

the on status when its driving signal is set (‘1’)

while it is in off status when the driving signal is re-

set (‘0’).

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