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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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L9805 датащи(PDF) 81 Page - STMicroelectronics |
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L9805 датащи(HTML) 81 Page - STMicroelectronics |
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81 / 103 page  81/103 L9805 Figure 42. Example - Power Bridge Waveform, PWM Up Brake Driving Mode 5.8.6 Register Description The power section is controlled by the microcon- troller through the following register: POWER BRIDGE CONTROL STATUS REGIS- TER (PBCSR) Address: 0021h - Read/Write Reset Value: 00000000 Bit 0 = EN: Power Bridge enable. When reset the bridge is disabled and OUTL and OUTR are in high impedance condition. Bit 1= PWM_EN: PWM driving enable. When reset the bridge is driven directly by IN1 and IN2 bit (Di- rect Mode). When set the driving is made by PWM1 and/or PWM2 bit according to the Opera- tion Mode selected by IN1 and IN2 bit. Bit 2= IN1: Left Half Bridge control bit if PWM_EN=0, driving mode selection bit if PWM_EN=1. Bit 3= IN2: Right Half Bridge control bit if PWM_EN=0, driving mode selection bit if PWM_EN=1. The following table summarizes the driving mode selection made by PWM_EN, IN1 and IN2 bit Bit 4= DIR: Direction bit. This bit is meaningless when PWM_EN=0. When PWM_EN is set the DIR bit controls the “driving direction” of the bridge. In order to implement a precise control of the direc- tion changes, DIR value is latched by the rising edge of the pwm signal driving the bridge. When the signal does not have edges (i.e. pwm = 0% or 100%) the DIR bit can not be latched and the driv- ing direction does not change even changing DIR bit in BCSR. Bit 5= SC: Short Circuit flag (read only) Bit 6= OVT: Overtemperature flag (read only) Bit 7= PIE: Power section interrupt enable. PWM1 DIR UL DL UR DR OUTL OUTR 70 PIE OVT SC DIR IN2 IN1 PWM_ EN EN PWM_EN IN1 IN2 Driving Mode 0 X X Direct 1 0 0 PWM1 Up Braking 1 0 1 PWM1 Down Braking 1 1 0 PWM1 Symmetrical 1 1 1 PWM1/PWM2 |
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