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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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L9805 датащи(PDF) 12 Page - STMicroelectronics |
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L9805 датащи(HTML) 12 Page - STMicroelectronics |
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12 / 103 page  12/103 L9805 2 CENTRAL PROCESSING UNIT 2.1 INTRODUCTION The CPU has a full 8-bit architecture. Six internal registers allow efficient 8-bit data manipulation. The CPU is capable of executing 63 basic instruc- tions and features 17 main addressing modes. 2.2 CPU REGISTERS The 6 CPU registers are shown in the program- ming model in Figure 2, on page 12. Following an interrupt, all registers except Y are pushed onto the stack in the order shown in Figure 3, on page 13. They are popped from stack in the re- verse order. The Y register is not affected by these automatic procedures. The interrupt routine must therefore handle Y, if needed, through the PUSH and POP instructions. Accumulator (A). The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calcula- tions as well as data manipulations. Index Registers (X and Y). These 8-bit registers are used to create effective addresses or as tem- porary storage areas for data manipulation. The Cross-Assembler generates a PRECEDE instruc- tion (PRE) to indicate that the following instruction refers to the Y register. Program Counter (PC). The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. Figure 2. Organization of Internal CPU Registers ACCUMULATOR: X INDEX REGISTER: Y INDEX REGISTER: STACK POINTER: CONDITION CODE REGISTER: PROGRAM COUNTER: X = Undefined 15 RESET VALUE: 70 XX XXX XXX RESET VALUE: 70 1X 11X 1X X 1C 1 1 HI NZ RESET VALUE = RESET VECTOR @ FFFEh-FFFFh RESET VALUE: 70 XX XXX XXX RESET VALUE: 70 XX XXXXXX 70 15 70 01 00 0000 RESET VALUE =0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 |
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