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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AX99100QF датащи(PDF) 69 Page - ASIX Electronics Corporation |
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AX99100QF датащи(HTML) 69 Page - ASIX Electronics Corporation |
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69 / 70 page  69 AX99100 PCIe to Multi I/O Controller Copyright © 2016 ASIX Electronics Corporation. All rights reserved. 6 Ordering Information Part Number Description AX99100 QF 68-pin QFN lead Free package, commercial temperature range: 0 to 70°C. AX99100 QI 68-pin QFN lead Free package, Industrial temperature range: -40 to 85°C. 7 Revision History Revision Date Comments V0.20 2016/04/18 Preliminary release. V0.21 2016/04/22 1. Added some descriptions for offset 0x55 bit2~6 in Section 3.3.1. 2. Changed offset 0x20 and 0x2A, Active 0/1 to Low/High in Section 3.3.2. 3. Added offset 0x5A~0x56 as Reserved fields in Section 3.3.2. 4. Added some descriptions for Local Address Space 0/1 Timing Setting, Local Address Space 0/1 Address Setting in Section 3.3.2. V0.22 2016/04/29 1. Changed offset 0x14 from 0xFF to 0xFD, offset 0x58 from 1 to 00 and offset 0x5B from 0x9F to 0xA2 in Table 3-7. 2. Added offset 0x53 ~ 0x54 and 0x56 in Table 3-4, Table 3-5 and section 3.3.1. 3. Added more descriptions in section 3.3 and 3.3.4. V0.23 2016/05/06 1. Changed the offset 0x56 naming from “PCIe Function Enable” to “Global Setting” in Table 3-4 and Table 3-5. V0.24 2016/06/06 1. Changed the offset 0x58 from 0x01 to 0x00 for LB mode in Table 3-6. 2. Changed bit11:10 to “Reserved” for offset 0x21~0x20 and 0x2B~0x2A in section 3.3.2. |
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