AX99100QF datasheet(38/70 Pages) ASIX

38 / 70 page

AX99100

PCIe to Multi I/O Controller

Bus Endian and Alignment for Local Address Space 0

When data bus width is 16-bit,

1: Big endian

0: Little endian

When data bus width is 8-bit,

1: Data place to/from DA[15:8]

0: Data place to/from DA[7:0]

Hardware Default Value: 0x0

Data Bus Width for Local Address Space 0

1: Bus width 16-bit width

0: Bus width 8-bit width

Hardware Default Value: 0x1

ALE Insertion Enable for Local Address Space 0

1: Enable ALE insertion

0: Disable ALE insertion

Note: This bit should be set to ‘1’ when bit7 of “Local Bus Interrupt Enable/Miscellaneous Setting”,

offset 0x19~0x18, is ‘1’.

Hardware Default Value: 0x0

Chip Select (CS0n) Enable for Local address Space 0

1: Enable Local Address Space 0 Chip Select

0: Disable Local Address Space 0 Chip Select

Hardware Default Value: 0x1

Local address Space 0 Enable

1: Enable the address mapping from PCIe BAR0 access to Local Address Space 0.

0: Disable the address mapping.

Hardware Default Value: 0x1

11:10

Reserved

Hardware Default Value: 0x3

Burst Read Enable for Local Address Space 0

1: Enable burst read access

0: Disable burst read access

Hardware Default Value: 0x1

14:13

Reserved

Hardware Default Value: 0x0

BAR0 Enable

1: Enable BAR0 access

0: Disable BAR0 access even offset 0x1B~0x1A, Local Bus PCIe BAR0 Range, are valid.

Hardware Default Value: 0x1

AX99100QF датащи(PDF) 38 Page - ASIX Electronics Corporation

AX99100QF датащи(HTML) 38 Page - ASIX Electronics Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

датащи скачать

ссылки URL