TPS2480PW datasheet(4/60 Pages) TI2

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TPS2480

TPS2481

SLUS939B – APRIL 2010 – REVISED DECEMBER 2010

www.ti.com

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Supply Current (VCC)

Enabled

VEN = Hi VSENSE = VOUT = VVCC

450

1000

IVCC

Disabled

VEN = Lo VSENSE = VVCC = VOUT = 0

250

Quiescent current

operating

0.7

1.0

IVS

Quiescent current

Power down mode

VPOR

Power On reset threshold

Current Sense Input (SENSE)

ISENSE

Input bias current

VSENSE = VVCC VOUT = VVCC

7.5

Reference Voltage Output (VREF)

VREF

Reference voltage

0 < IVREF < 1 mA

3.9

4.1

Power Limiting Input (PROG)

Input bias current; device

IPROG

0 < VPROG < 4 V VEN = 48 V

enabled; sourcing or sinking

Pulldown resistance; device

RPROG

IPROG = 200 mA; VEN = 0 V

375

600

Ω

disabled

Power Limiting and Current Limiting (SENSE)

Current sense threshold

VPROG = 2.4 V; VOUT = 0 V or VPROG = 0.9 V; VOUT

VCL

V(VCC-SENSE) with power

= 30 V; VVCC = 48 V

limiting trip

Current sense threshold

VSENSE

V(VCC-sense) without power

VPROG = 4 V; VSENSE = VOUT

limiting trip

VPROG = 4 V; VOUT = VSENSE; V(VCC-SENSE): 0

Large overload response time

tF_TRIP

rising to 200 mV; C(GATE-OUT) = 2 nF; V(GATE-OUT) =

1.2

to GATE low

1 V

Timer Operation (TIMER)

VTIMER = 0 V

15.0

25.0

34.0

ISOURCE

Charge current (sourcing)

VTIMER = 0 V; TJ = 25°C

20.0

25.0

30.0

VTIMER = 5 V

1.50

2.5

3.70

ISINK

Discharge current (sinking)

VTIMER = 5 V; TJ = 25°C

2.10

2.5

3.10

TIMER upper threshold

3.9

4.0

4.1

voltage

TIMER lower reset threshold

TPS2481 only

0.96

1.0

1.04

voltage

DRETRY

Fault retry duty cycle

TPS2481 only

0.5%

0.75%

1.0%

Gate Drive Output (GATE)

IGATE

GATE sourcing current

VSENSE = VVCC; V(GATE-OUT) = 7 V; VEN = Hi

VEN = Lo; VGATE = VVCC

1.8

2.4

2.8

GATE sinking current

VEN = Hi; VGATE = VVCC; V(VCC-SENSE)³ 200 mV

125

250

VGATE-OUT GATE output voltage

Propagation delay: EN going

VEN = 0 → 2.5 V, 50% of VEN to 50% of VGATE,

tD_ON

true to GATE output high

VOUT = VVCC, R(GATE-OUT) = 1 MOhm

Propagation delay: EN going

VEN = 2.5 V → 0 V, 50% of VEN to 50% of VGATE,

tD_OFF

false (0 V) to GATE output

0.5

VOUT = VVCC, R(GATE-OUT) = 1 MΩ, tFALL < 0.1 ms

low

Propagation delay: TIMER

VTIMER: 0 → 5 V, tRISE < 0.1 ms. 50% of VTIMER to

0.8

expires to GATE output low

50% of VGATE, VOUT = VCC , R(GATE-OUT) = 1 MΩ,

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