TPS2480PW datasheet(29/60 Pages) TI2

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TPS2480

TPS2481

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SLUS939B – APRIL 2010 – REVISED DECEMBER 2010

Serial Bus Address

To communicate with the TPS2480/81, the master must first address slave devices via a slave address byte. The

slave address byte consists of seven address bits, and a direction bit indicating the intent of executing a read or

write operation.

The TPS2480/81 have two address pins, A0 and A1. Table 2 describes the pin logic levels for each of the 16

possible addresses. The state of pins A0 and A1 is sampled on every bus communication and should be set

before any activity on the interface occurs. The address pins are read at the start of each communication event.

Table 2. TPS2480/81 Address Pins and

Slave Addresses

SLAVE ADDRESS

GND

1000000

GND

VS+

1000001

GND

SDA

1000010

GND

SCL

1000011

VS+

GND

1000100

VS+

1000101

VS+

SDA

1000110

VS+

SCL

1000111

SDA

GND

1001000

SDA

VS+

1001001

SDA

1001010

SDA

SCL

1001011

SCL

GND

1001100

SCL

VS+

1001101

SCL

SDA

1001110

SCL

1001111

Serial Interface

The TPS2480/81 operates only as a slave device on the I2C bus and SMBus. Connections to the bus are made

via the open-drain I/O lines SDA and SCL. The SDA and SCL pins feature integrated spike suppression filters

and Schmitt triggers to minimize the effects of input spikes and bus noise. The TPS2480/81 support the

transmission protocol for fast (1 kHz to 400 kHz) and high-speed (1 kHz to 3.4 MHz) modes. All data bytes are

transmitted most significant byte first.

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