TPS2480PW datasheet(30/60 Pages) TI2

30 / 60 page

TPS2480

TPS2481

SLUS939B – APRIL 2010 – REVISED DECEMBER 2010

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Writing To/Reading From The TPS2480/81

Accessing a particular register on the TPS2480/81 is accomplished by writing the appropriate value to the

LOW. Every write operation to the TPS2480/81 requires a value for the register pointer.

Writing to a register begins with the first byte transmitted by the master. This byte is the slave address, with the

R/W bit LOW. The TPS2480/81 then acknowledges receipt of a valid address. The next byte transmitted by the

master is the address of the register to which data will be written. This register address value updates the

pointer. The TPS2480/81 acknowledges receipt of each data byte. The master may terminate data transfer by

generating a START or STOP condition.

When reading from the TPS2480/81, the last value stored in the register pointer by a write operation determines

which register is read during a read operation. To change the register pointer for a read operation, a new value

must be written to the register pointer. This write is accomplished by issuing a slave address byte with the R/W

bit LOW, followed by the register pointer byte. No additional data are required. The master then generates a

START condition and sends the slave address byte with the R/W bit HIGH to initiate the read command. The

next byte is transmitted by the slave and is the most significant byte of the register indicated by the register

pointer. This byte is followed by an Acknowledge from the master; then the slave transmits the least significant

byte. The master acknowledges receipt of the data byte. The master may terminate data transfer by generating a

Not-Acknowledge after receiving any data byte, or generating a START or STOP condition. If repeated reads

from the same register are desired, it is not necessary to continually send the register pointer bytes; the

TPS2480/81 retains the register pointer value until it is changed by the next write operation.

Figure 20 and Figure 21 show write and read operation timing diagrams, respectively. Note that register bytes

are sent most-significant byte first, followed by the least significant byte. Figure 22 shows the timing diagram for

the SMBus Alert response operation. Figure 23 illustrates a typical register pointer configuration.

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