TPS2480PW datasheet(35/60 Pages) TI2

35 / 60 page

TPS2480

TPS2481

www.ti.com

SLUS939B – APRIL 2010 – REVISED DECEMBER 2010

All current and power calculations are performed in the background and do not contribute to conversion time;

conversion times shown in the Electrical Characteristics table can be used to determine the actual conversion

time.

Power-Down mode reduces the quiescent current and turns off current into the TPS2480/81 inputs, avoiding any

supply drain. Full recovery from Power-Down requires 40 ms. ADC Off mode (set by the Configuration Register,

MODE bits) stops all conversions.

In triggered mode, the external Convert line becomes active. Convert commands are initiated by taking the

Convert line low for a minimum of 4 ms. The Convert line may be connected high when unused. Any re-trigger of

the Convert line during a conversion is ignored, and the Convert line state is disregarded until the conversion

ends. There are several available triggered modes; however, all conversions are performed repeatedly up to the

number set in the Averaging function (Configuration Register, BADC and SADC bits).

If the Convert line is held low, writing any of the triggered convert modes into the Configuration Register (even if

the desired mode is already programmed into the register) triggers a single-shot conversion.

Although the TPS2480/81 can be read at any time, and the data from the last conversion remain available, the

Conversion Ready bit (Status Register, CNVR bit) is provided to help co-ordinate one-shot or triggered

conversions. The Conversion Ready bit is set after all conversions, averaging, and multiplication operations are

complete.

The Conversion Ready bit clears under these conditions:

1. Writing to the Configuration Register, except when configuring the MODE bits for Power Down or ADC off

(Disable) modes;

2. Reading the Status Register; or

3. Triggering a single-shot conversion with the Convert pin.

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TPS2480PW датащи(PDF) 35 Page - Texas Instruments