TPS2480PW datasheet(24/60 Pages) TI2

24 / 60 page

VCC

CHARGE

GATE

ISS

VCC

TPS2480

TPS2481

SLUS939B – APRIL 2010 – REVISED DECEMBER 2010

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Alternative Inrush Designs

Gate Capacitor (dV/dt) Control

The TPS2480/81 can be configured to provide a linear dV/dt turn on characteristic. The load capacitor charging

current ICHARGE, is controlled by a single capacitor from the GATE terminal to ground. M1 operates as a source

follower (following the gate voltage) in this implementation. Choose a charge time, tON, based on the load

capacitor, CO input voltage VI, and desired charge current. When power limiting is used (VPROG < VREF) choose

ICHARGE to be less than PLIM /VVCC to prevent the fault timer from starting. The fault timer starts only if power or

current limit is invoked.

(26)

Use the following equation to select the gate capacitance, CG. CISS is the gate capacitance of M1, and IGATE is

the TPS2480/81 nominal gate charge current. As shown in Figure 17, a series resistor of about 1 k

Ω should be

used in series with CG.

(27)

If neither power nor current limit faults are invoked during turn on, CT can be chosen for fast transient turn off

response using the M1 SOA curve. Choose the single pulse time conservatively from the M1 SOA curve using

maximum operating voltage and maximum trip current.

PROG Inrush Control

A capacitor can be connected from the PROG pin to ground to reduce the initial current step seen in Figure 12.

This method maintains a relatively fast turn-on time without the drawbacks of a gate-to-ground capacitor that

include increased short circuit response time and less predictable gate clamping.

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