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INA745AIRELR датащи(PDF) 7 Page - Texas Instruments

номер детали INA745AIRELR
подробное описание детали  INA745x 40V, 16-Bit, Precision I2C Output Digital Power Monitor With EZShunt™ Technology
PDF  50 Pages
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производитель  TI2 [Texas Instruments]
домашняя страница  https://www.ti.com
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INA745AIRELR датащи(HTML) 7 Page - Texas Instruments

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5.6 Timing Requirements (I2C)
MIN
NOM
MAX
UNIT
I2C BUS (FAST MODE)
F(SCL)
I2C clock frequency
1
400
kHz
t(BUF)
Bus free time between STOP and START conditions
600
ns
t(HDSTA)
Hold time after a repeated START condition. After this period, the first
clock is generated.
100
ns
t(SUSTA)
Repeated START condition setup time
100
ns
t(SUSTO)
STOP condition setup time
100
ns
t(HDDAT)
Data hold time
10
900
ns
t(SUDAT)
Data setup time
100
ns
t(LOW)
SCL clock low period
1300
ns
t(HIGH)
SCL clock high period
600
ns
tF
Data fall time
300
ns
tF
Clock fall time
300
ns
tR
Clock rise time
300
ns
I2C BUS (HIGH-SPEED MODE)
F(SCL)
I2C clock frequency
10
2940
kHz
t(BUF)
Bus free time between STOP and START conditions
160
ns
t(HDSTA)
Hold time after a repeated START condition. After this period, the first
clock is generated.
100
ns
t(SUSTA)
Repeated START condition setup time
100
ns
t(SUSTO)
STOP condition setup time
100
ns
t(HDDAT)
Data hold time
10
125
ns
t(SUDAT)
Data setup time
20
ns
t(LOW)
SCL clock low period
200
ns
t(HIGH)
SCL clock high period
60
ns
tF
Data fall time
80
ns
tF
Clock fall time
40
ns
tR
Clock rise time
40
ns
5.7 Timing Diagram
SCL
SDA
t
(LOW)
t
R
t
F
t
(HDSTA)
t
(HDSTA)
t
(HDDAT)
t
(SUDAT)
t
(HIGH)
t
(SUSTA)
t
(SUSTO)
t
(BUF)
S
S
P
P
Figure 5-1. I2C Timing Diagram
www.ti.com
INA745A, INA745B
SBOSAC3B – JULY 2023 – REVISED AUGUST 2025
Copyright © 2025 Texas Instruments Incorporated
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Product Folder Links: INA745A INA745B



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