INA745AIRELR datasheet(20/50 Pages) TI2

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When the ALERT pin is configured to report the ADC conversion complete event, the ALERT pin becomes

a multipurpose reporting output. Figure 6-11 shows an example where the device reports ADC conversion

complete events while the INA745x device is subject to an overcurrent event, bus undervoltage event,

overtemperature event and over power-limit event.

Current

Temperature

Bus Voltage

ALERT

(ALATCH = 0)

(APOL = 0)

(CNVR = 1)

Power

Current Over Limit Threshold

Bus Under Voltage Threshold

Over Temp Threshold

Power Over Limit Threshold

BUV

SET

COL

SET

BUV

CLEAR

COL

BUV

SET

COL

CLEAR

BUV

SET

BUV

SET

- No diag. error -

Conversion Complete

Reported

Figure 6-11. Multi-Alert Configuration

6.4 Device Functional Modes

6.4.1 Shutdown Mode

In addition to the two conversion modes (continuous and triggered), the device also has a shutdown mode

(selected by the MODE bits in ADC_CONFIG register) that reduces the quiescent current to less than 5µA and

turns off current into the device inputs, reducing the impact of supply drain when the device is not being used.

The registers of the device can be written to and read from while the device is in shutdown mode. The device

remains in shutdown mode until another triggered conversion command or continuous conversion command is

received.

The device can be triggered to perform conversions while in shutdown mode. When a conversion is triggered,

the ADC starts the conversion. When the conversion completes, the device returns to the shutdown state.

Note that the shutdown current is specified with an inactive communications bus. Active clock and data activity

increases the current consumption as a function of the bus frequency.

6.4.2 Power-On Reset

Power-on reset (POR) is asserted when VS drops below 1.26V (typical) at which all of the registers are reset to

the default values. A manual device reset can be initiated by setting the RST bit in the CONFIG register. The

default power-up register values are shown in the reset column for each register description. Links to the register

descriptions are shown in Register Maps.

6.5 Programming

6.5.1 I2C Serial Interface

The INA745x operates only as a target on both the SMBus and I2C interfaces. Connections to the bus are made

through the open-drain SDA and SCL lines. The SDA and SCL pins feature integrated spike suppression filters

and Schmitt triggers to minimize the effects of input spikes and bus noise. Although the device integrates spike

suppression into the digital I/O lines, proper layout techniques help minimize the amount of coupling into the

communication lines. This noise introduction can occur from capacitive coupling signal edges between the two

INA745A, INA745B

SBOSAC3B – JULY 2023 – REVISED AUGUST 2025

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