INA745AIRELR datasheet(21/50 Pages) TI2

21 / 50 page

communication lines themselves or from other switching noise sources present in the system. Routing traces in

parallel with ground in between layers on a printed circuit board (PCB) typically reduces the effects of coupling

between the communication lines. Shielded communication lines reduce the possibility of unintended noise

coupling into the digital I/O lines that can be incorrectly interpreted as start or stop commands.

The INA745x supports the transmission protocol for fast mode (1kHz to 400kHz) and high-speed mode (1kHz to

2.94MHz). All data bytes are transmitted most significant byte first and follow the SMBus 3.0 transfer protocol.

To communicate with the INA745x , the controller must first address targets through a target address byte. The

target address byte consists of seven address bits and a direction bit that indicates whether the action is to be a

read or write operation.

The device has two address pins, A0 and A1. Table 6-2 lists the pin logic levels for each of the 16 possible

addresses. The device samples the state of pins A0 and A1 on every bus communication. Establish the pin state

before any activity on the interface occurs. When connecting the SDA pin to either A0 or A1 to set the device

address, an additional hold time of 100ns is required on the MSB of the I2C address to provide correct device

addressing.

Table 6-2. Address Pins and Target Addresses

TARGET DEVICE ADDRESS

GND

1000000

GND

1000001

GND

SDA

1000010(1)

GND

SCL

1000011

GND

1000100

1000101

SDA

1000110(1)

SCL

1000111

SDA

GND

1001000(1)

SDA

1001001(1)

SDA

1001010(1)

SDA

SCL

1001011(1)

SCL

GND

1001100

SCL

1001101

SCL

SDA

1001110(1)

SCL

1001111

(1)

Any address using SDA requires an initial hold time of 100ns on the MSB of the address.

6.5.1.1 Writing to and Reading Through the I2C Serial Interface

Accessing a specific register on the INA745x is accomplished by writing the appropriate value to the register

pointer. Refer to Register Maps for a complete list of registers and corresponding addresses. The value for the

bit low. Every write operation to the device requires a value for the register pointer.

Writing to a register begins with the first byte transmitted by the controller. This byte is the target address,

with the R/W bit low. The device then acknowledges receipt of a valid address. The next byte transmitted by

the controller is the address of the register to be accessed. This register address value updates the register

pointer to the desired internal device register. The next two bytes are written to the register addressed by the

by generating a start or stop condition.

When reading from the device, the last value stored in the register pointer by a write operation determines which

www.ti.com

INA745A, INA745B

SBOSAC3B – JULY 2023 – REVISED AUGUST 2025

Submit Document Feedback

Product Folder Links: INA745A INA745B

INA745AIRELR датащи(PDF) 21 Page - Texas Instruments

INA745AIRELR датащи(HTML) 21 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

датащи скачать

ссылки URL