INA745AIRELR datasheet(17/50 Pages) TI2

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the input measurements as described above, after which the ADC enters into shutdown mode until another

single-shot trigger is generated by writing to the MODE bits. Writing the MODE bits interrupts and restarts

triggered or continuous conversions that are in progress. The values from the device can be read at any time

because data from the last conversion remains available until the next conversion is complete. The Conversion

Ready flag is set after all conversions and averaging are complete.

The Conversion Ready flag (CNVRF) clears under these conditions:

• Writing to the ADC_CONFIG register (except for selecting shutdown mode); or

• Reading the DIAG_ALRT Register

While the INA745x device is used in either one of the conversion modes, a dedicated digital engine is calculating

the current, power, charge and energy values in the background as described in Internal Measurement

and Calculation Engine. In triggered mode, the accumulation registers (ENERGY and CHARGE) are invalid,

as the device does not keep track of elapsed time. For applications that require critical measurements in

regards to accumulation of time for energy and charge measurements, the device must be configured to use

continuous conversion mode, as the accumulated results are continuously updated and can provide true system

representation of charge and energy consumption in a system. All of the calculations are performed in the

background and do not contribute to conversion time.

For applications that must synchronize with other components in the system, the INA745x conversion can be

delayed by programming the CONVDLY bits in the CONFIG register in the range between 0ms (no delay)

and 510ms. The resolution in programming the conversion delay is 2ms. The conversion delay is set to

0ms by default. Conversion delay can assist in measurement synchronization when multiple external devices

are used for voltage or current monitoring purposes. In applications where time-aligned voltage and current

measurements are needed, two devices can be used with the current measurement delayed such that the

external voltage and current measurements occur at approximately the same time. Keep in mind that even

though the internal time base for the ADC is precise, synchronization is lost over time due to internal and

external time base mismatch.

6.3.5.1 Low Latency Digital Filter

The device integrates a low-pass digital filter that performs both decimation and filtering on the ADC output data,

which helps with noise reduction. The digital filter is automatically adjusted for the different output data rates and

always settles within one conversion cycle. The user has the flexibility to choose different output conversion time

periods TCT from 50µs to 4.12ms. With this configuration the first amplitude notch is determined by the selected

conversion time period and defined as fNOTCH= 1 / TCT) while in single conversion mode. This means that the

filter cut-off frequency scales proportionally with the data output rate. Figure 6-8 shows the filter response when

the 1.052ms conversion time period is selected.

−60

−50

−40

−30

−20

−10

100

10k

100k

Frequency (Hz)

G001

Conversion time = 1.052ms

Figure 6-8. ADC Frequency Response

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INA745A, INA745B

SBOSAC3B – JULY 2023 – REVISED AUGUST 2025

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