be written to the register pointer. This write is accomplished by issuing a target address byte with the R/W bit

low, followed by the register pointer byte. No additional data are required. The controller then generates a start

condition and sends the address byte for the target with the R/W bit high to initiate the read command. The next

byte is transmitted by the target and is the most significant byte of the register indicated by the register pointer.

This byte is followed by an Acknowledge from the controller; then the target transmits the least significant byte.

The controller can or can not acknowledge receipt of the second data byte. The controller can terminate data

transfer by generating a Not-Acknowledge after receiving any data byte, or generating a start or stop condition.

If repeated reads from the same register are desired, continually sending the register pointer bytes is not

necessary; the device retains the register pointer value until the value is changed by the next write operation.

Figure 6-12 shows the write operation timing diagram. Figure 6-13 shows the read operation timing diagram.

These diagrams are shown for reading and writing to 16-bit registers.

Register bytes are sent most significant byte (MSB) first, followed by the least significant byte (LSB).

Frame 1 Two-Wire Target Address Byte

Frame 2 Register Pointer Byte

Start By

Controller

ACK By

Target

ACK By

Target

1

9

1

ACK By

Target

1

D15 D14

D13

D12 D11 D10

D9

D8

9

9

SDA

SCL

1

0

0

A3

A2

A1

A0

R/W

P7

P6

P5

P4

P3

P2

P1

P0

Frame 4 Data LSByte

Frame 3 Data MSByte

ACK By

Target

Stop By

Controller

1

D7

D6

D5

D4

D3

D2

D1

D0

9

A.

The value of the target address byte is determined by the settings of the A0 and A1 pins. Refer to Table 6-2.

B.

The device does not support packet error checking (PEC) or perform clock stretching.

Figure 6-12. Timing Diagram for Write Word Format

Frame 1 Two-Wire Target Address Byte

Frame 2 Data MSByte

1

Start By

Controller

ACK By

Target

ACK By

Controller

From

Target

1

9

1

9

SDA

SCL

0

0

A3

R/W

D15 D14 D13

D12

D11 D10

D9

D8

A2

A1

A0

Frame 3 Data LSByte

Stop

No ACK By

Controller

From

Target

1

9

D7

D6

D5

D4

D3

D2

D1

D0

A.

The value of the target address byte is determined by the settings of the A0 and A1 pins. Refer to Table 6-2.

B.

Read data is from the last register pointer location. If a new register is desired, the register pointer must be updated. See Figure 6-14.

C.

ACK by the controller can also be sent.

D.

The device does not support packet error checking (PEC) or perform clock stretching.

Figure 6-13. Timing Diagram for Read Word Format

Frame 1 Two-Wire Target Address Byte

Frame 2 Register Pointer Byte

1

Start By

Controller

ACK By

Target

ACK By

Target

1

9

1

9

SDA

SCL

0

0

A3

A2

A1

A0

R/W

P7

P6

P5

P4

P3

P2

P1

P0

Stop

A.

The value of the target address byte is determined by the settings of the A0 and A1 pins. Refer to Table 6-2.

Figure 6-14. Typical Register Pointer Set

INA745A, INA745B

SBOSAC3B – JULY 2023 – REVISED AUGUST 2025

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