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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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INA745AIRELR датащи(PDF) 38 Page - Texas Instruments |
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INA745AIRELR датащи(HTML) 38 Page - Texas Instruments |
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38 / 50 page  8.4.2 Layout Example 2 1 7 14 Address Lines A1, A0 via to connect directly to VS, GND, SDA, or SCL to set device address I2C bus connections for clock and data (pullup resistors not shown) Place Vias connecting to inner or bottom layers as close as possible to the device. The number of vias required depends on operational current and ambient conditions Device Bypass Capacitor TI Device IS+ IS 1. All vias close to the pin pads must be tented. 2. All vias are either 8 mil/18 mil or 15 mil/25 mil with a 5 mill annular ring. 3. The distance between the IS+ and IS– power pours is 8 mil. 4. See EVM User's Guide for more specific layout recommendations and layers. Figure 8-5. INA745x Layout Example INA745A, INA745B SBOSAC3B – JULY 2023 – REVISED AUGUST 2025 www.ti.com 38 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: INA745A INA745B |
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