L9969X datasheet(42/70 Pages) STMICROELECTRONICS

42 / 70 page

Figure 29. Standard SPI frame

Write access

(16 Bit Frame)

Read access

(16 Bit Frame)

MSB

LSB

8 bit Instruction

8 bit Data

MSB

LSB

MSB

LSB

8 bit Instruction

8 bit Data

MSB

LSB

Check Byte

(zz + 6 bit)

Check Byte

(zz + 6 bit)

00000000

XXXXXXXX

Since the coding of the SPI instructions is done in such a way that at least at bit 5 it is clear, whether a reading or

a writing instruction is sent, and moreover, the instructions are not using the LSB of the instruction, there is at

least a duration of one bit left in order to provide the requested data for the SO.

3.2.7.3

Characteristics of the SPI interface

The characteristics of the SPI interface are the following:

•

During active reset conditions: the SPI is driven in its default state. When reset becomes inactive, the

state machine enters in a wait state for the next instruction. During active reset conditions the output SO is

in high impedance state (tristate).

•

If the slave-select signal at NSS is inactive (high): the state machine is forced to enter the wait state,

that is the state machine waits for the following instruction.

•

During active (low) state of the select signal SS: the falling edge of the serial clock signal SCK will be

used to latch the input data at SI. Output data at SO are driven with the rising edge of SCK. Further

processing of the data according to the instruction (that corresponds to the modification of the internal

registers) will be triggered by the rising edge of the NSS signal.

•

Chip address: in order to establish the option of extended addressing, the uppermost two bits of the

instruction-byte (that is the first two SI-bits of a frame) are reserved to send a chip address.

For future orientation, a configurable chip-address is requested. This should be achieved by connecting the

chip-address register-bits to an electrical low or high potential onto the silicon. The default chip-address (as

specified in Section 3.2.7.4: SPI Instruction) should always be 00hex. However, a switch-over, by modifying

the bond-wire configuration onto the silicon should be possible later on for a dedicated derivate. As

alternative a mask option or fuse can be also used.To avoid a bus conflict the output SO must stay in high

impedance state during the addressing phase of a frame (that is until the address bits are recognized as

valid chip address). If the chip address does not match, the corresponding access will be ignored and SO

remains high impedance for the complete frame regardless of the frame type that is applied. Even in case

the lower instruction bits match to a valid instruction, there is no impact on internal registers or any

functions (including the Transfer Failure Message).

•

Check byte: during the receiving of an SPI instruction, the H-bridge transmits a check byte via the output

SO to the controller. This byte indicates the correctness of the operation of the SPI. It contains an initial bit

pattern and a flag indicating possible invalid instruction of the previous access.

•

Read and write access: during a read access the data bits at the SPI input SI are rejected/ignored. During

a valid write access the SPI will transmit the data byte “00hex” at the output SO after having sent the check

byte. When a Bit in the Register is cleared during Read-Access this will be done when the communication

is finished successfully (rising edge of SS after 16 bits).

L9969x

Functional description

DS14029 - Rev 6

page 42/70

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