L9969X datasheet(13/70 Pages) STMICROELECTRONICS

13 / 70 page

2.6.1

Power-ON reset

VDD is internally monitored, to keep the output stages in tristate in case VDD is incorrect.

Two internal monitoring/resetting sources are implemented:

•

The internal reset function in the H-bridge if VDD is decreasing down to VDD_RES. That function resets the

SPI registers, switches the output stages to tristate and switches NABE to low.

•

The internal VDD monitoring, that is working, if the VDD > VDD_POR for longer than tPOR. In this case,

the SPI is working; the VDD monitoring is active and sets the SPI registers, switches the output stages to

tristate and switches NABE to low, if VDD is incorrect. In any cases, after a Power-ON Reset, the H-bridge

is completely functional again, but the outputs are disabled. They can only be enabled by ENDISR.

5 V < VBATT < 18 V, TJ= -40 °C to 150 °C, unless otherwise specified.

Table 10. VDD monitoring thresholds

Symbol

Parameter

Condition Min Typ Max Unit

VDD_RES

VDD Undervoltage Threshold (VDD: ‘H’ → ’L’) Below this threshold the device

is in reset state, all registers are cleared.

3.3 3.6

3.9

VDD_POR

Power On Reset Threshold (VDD: ‘L’ → ’H’) Below this threshold the device is

in reset state, all registers are cleared. The device starts operation (VDD

monitoring forces stages off) not later than tPOR, when VDD is rising above this

threshold. SPI is functional.

3.5 3.8

4.1

tPOR

Power On Reset Extension Time

1000

µs

2.6.2

NABE and VDD monitoring

2.6.2.1

General functions of VDD monitoring

VDD is measured with reference to pin GNDABE. Inside the H-bridge, GNDABE is routed separately to avoid

internal cross talking from power lines.

The state of VDD monitoring is stored in STATCON_REG and is read/write via SPI.

VDD monitoring detects faulty supply voltages at VDD. It disables the output stages but does not reset registers

DIA_REG1, DIA_REG2, CONFIG_REG or STATCON_REG.

In case of VDD failure, the output stages are switched off, even if the voltage at pin NABE is a high level, for

example because of an external short circuit to VDD or to the battery voltage (up to 18 V).

OUT1 and OUT2 cannot be switched on in over or undevoltage condition at VDD.

POR (VDD < VDD_RES) switches off all output stages without delay.

Detailed information (differentiation of over and undervoltage detection) is possible by SPI interface.

L9969x

Electrical specifications

DS14029 - Rev 6

page 13/70

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