L9969X datasheet(16/70 Pages) STMICROELECTRONICS

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A low logic level at “NABE” and/or a high logic level at “DIS” switch off all output stages. In this case the access to

the SPI is possible and the bit NABE_DIS in the DIA_REG1 is set to low.

Two separate pins are provided for NABE and DIS. For safety reasons, these signals are routed separately and

ideally with a certain distance from each other on the silicon.

2.6.2.6

Testing of VDD monitoring

VDD Monitoring cannot be switched off. The output stages are switched off by VDD monitoring if under or

overvoltage on VDD is detected. Testing of VDD monitoring is possible via SPI.

Testing of upper thresholds:

By writing STATCON_REG, bit CONFIG2 = 0, the VDD test mode is activated.

If STATCON_REG, bit CONFIG1 = 0, the upper VDD test threshold is lowered (overvoltage threshold is reduced

to VTEST_THH).

As a result, STATCON_REG, bit STATUS0 = 0 and DIA_REG1, bit NABE_DIS = 0.

Overvoltage is reported and pin NABE is pulled low.

Once the test routine is ended (CONFIG2 = 1) or the upper VDD test threshold is reset to its standard value,

STATUS0=1 (no overvoltage anymore) and NABE_DIS =1. Pin NABE is pulled high.

The same test routine can be performed with STATCON_REG, bit CONFIG0 = 1 (latching of overvoltage

condition). In that case, ending the test routine will not automatically reset bit NABE_DIS and pin NABE.

Testing of lower thresholds:

By writing STATCON_REG, bit CONFIG2 = 0, the VDD test mode is activated.

If STATCON_REG, bit CONFIG1 = 1, the lower VDD test threshold is lifted (undervoltage threshold is increased

to VTEST_THL).

As a result, STATCON_REG, bit STATUS1 = 0 and DIA_REG1, bit NABE_DIS = 0.

Undervoltage is reported and pin NABE is pulled low.

Once the test routine is ended (CONFIG2 = 1) or the lower VDD test threshold is reset to its standard value,

STATUS1=1 (no undervoltage anymore) and NABE_DIS =1. Pin NABE is pulled high.

Figure 9. Circuit diagram of VDD monitoring

L9969x

Electrical specifications

DS14029 - Rev 6

page 16/70

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