L9305 datasheet(26/107 Pages) STMICROELECTRONICS

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6.1.10

Dither synchronization

In variable frequency mode, the PWM switch-on events are not clock based and are dependent on frequency

control loop response. Therefore variable frequency mode is naturally asynchronous with respect to the dither

steps. However, it is still possible to synchronize dither with the variable frequency PWM control by synchronizing

with the actual PWM frequency. There are two options to sync the dither waveform. The two sync types are

shown below. Please, note that the function is not valid for fixed frequency operation since all dither steps are

synchronous with the PWM control frequency.

•

Dither SYNC Enable - register Channelx_DTHPGM1, bit D[14]

–

0 → Dither synch for variable frequency is disabled

–

1 → Dither synch for variable frequency is enabled

•

SYNC TYPE – register ChannelxDTHPGM1, bit D[13]

–

0 → All Dither Steps are synchronous with the PWM Period. In this case the time base for Dither

Step duration is the actual PWM period rather than the exact target set point PWM period

–

1 → The Dither Period starts synchronous with the actual PWM Period. Only for the initial step in the

dither period, the Tstep is delayed to the next switch on transition of the PWM period. The time of

such initial step may be longer than the programmed period.

6.2

Software current control

In this configuration the device works as a driver without internal current control but provides the average

measured load current to the MCU through register Channel_x.AVGCUR, bits D[13:0]. With the average current

feedback, the MCU can close the current control loop.

Figure 14. Software control configuration

INx

VS_SOL_x

LOADx

GND_SOL_x

EN_DR

Driver

Control

SPI

Current Sense

HS Driver

LS Driver

SPI

GADG2709181307PS

To avoid spurious switching of the external loads due to noise spikes on INx pins, a digital filter, LOADx_ton_res

and LOADx_toff_res (where “x” is related to selected channel), has been added to these pins.

Since the filter time is applied on each transition of the INx pin signal, OFF to ON and ON to OFF, the effect limits

the minimum period or maximum frequency of the signal delivered to the LOADx pin.

Channel state depends on the EN_DR input pin and the value of the Driver Configuration/Status SPI register

(Global.Solenoid Drivers Enable) as shown below.

Table 12. Solenoid driver channel status in software mode

EN_DR

Driver configuration status

Channel status

[1]

[0]

LOW

Driver Disabled, Off Diagnosis disabled and Masked

HIGH

Driver in Tristate, Off diagnosis can be switched on

L9305

Current control drivers

DS12774 - Rev 10

page 26/107

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