L9305 datasheet(52/107 Pages) STMICROELECTRONICS

52 / 107 page

Figure 27. SPI timings, thresholds 20% to 80% and viceversa

CSN

SCLK

SDO

MSB

LSB

SDI

MSB

LSB

tsclch

thclcl

tclh

tcll

tsclcl

thclch

tpchdz

tscld thcld

tcsdv

tSDO-trans

tpcld

GADG2609181548PS

9.7

SPI registers map table

SPI frame has an 8-bit address field and 16-bit data field, then the available address space consists of up to 256

different registers. Taking into account the logical and physical partition of the functions to be configured and

monitored by SPI interface, the address space has been divided in pages of 32 addresses each.

The table below shows the SPI page vs. macro function distribution.

Table 39. SPI page address mapping

Page ID[binary]

Macro Function

Address Space Name

SPI Base Address

[hex]

[binary]

000

Solenoid Channel 0

Channel_0_BaseAddress

0x00

0000 0000

001

Solenoid Channel 1

Channel_1_BaseAddress

0x20

0010 0000

010

Solenoid Channel 2

Channel_2_BaseAddress

0x40

0100 0000

011

Solenoid Channel 3

Channel_3_BaseAddress

0x60

0110 0000

100

unused

---

0x80

1000 0000

101

unused

---

0xA0

1010 0000

110

Global

Global_BaseAddress

0xC0

1100 0000

111

Fault and Test

Fault_Test_BaseAddress

0xE0

1110 0000

9.8

Global page

Global page contains general control/monitor registers.

Table 40. SPI global page register address mapping

Idx [hex]

0x00

Service enable

0x01

Solenoid drivers enable

0x02

Timeout SPI configuration

0x03

Fail safe pre-driver configuration

0x1F

Chip ID

L9305

SPI

DS12774 - Rev 10

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