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L9305 датащи(PDF) 15 Page - STMicroelectronics

номер детали L9305
подробное описание детали  Automotive 4-channel valve driver
PDF  107 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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5.4
Analog and digital supply (VDD)
The VDD pin provides the source voltage for all internal analog (V3V3A) and digital (V3V3D) circuits. An internal
start-up circuit connected to VDD initializes the internal regulators (V3V3A & V3V3D) once VDD reaches
VDD_UV threshold. V3V3A & V3V3D regulators are monitored for internal power on reset control (POR). VDD
input voltage is diagnosed for over and under voltage conditions. The status of this diagnostic is readable by SPI.
Please see Section 8.1.1: VDD over and under voltage diagnostics.
5.5
I/O supply (VDDIO)
VDDIO is the supply for all pins that interface with the external microcontroller. This pin must be connected to a
supply with the same voltage used by the microcontroller I/O, 3.3 V or 5.0 V. There is no monitoring function
associated with VDDIO.
5.6
Power-On reset
An internal power on reset circuit holds the device in a reset state if VDD goes below the under voltage threshold.
The power on reset is released once VDD is within normal operating range for the specified reset filter time
TPOR. The SPI interface can be accessed after the power on reset time.
The fault bit “POR_flag” in the SERVFLT1 register is set, when the device exits the reset state. This bit is cleared
automatically, whenever the SERVFLT1 register is accessed. Also RES_echo in PINSTATUS register is set, when
the device exits the reset state in case of Power-On reset event, despite the state of RESn pin. The
microcontroller can use these bits to determine if an internal or external reset has occurred.
A power on reset (POR) can also occur if any of the internal bandgap regulators or internal analog & digital
regulators are diagnosed as over or under voltage. Additional details on these and VDD monitoring can be found
in sections Section 8.1.1 and Section 8.1.4.
5.7
GND (GNDD, GNDA, GND_SOLx)
The L9305 has two low power ground connections, GNDD and GNDA. These connections are for internal analog
and digital control circuits. Exposed pad is connected to substrate and to GNDA. GNDD and GNDA are
connected through a pair of anti-parallel ESD diodes. The device has 4 power ground connections, GND_SOL0,
GND_SOL1, GND_SOL2 and GND_SOL3. All ground pins have open circuit detection. Additional details on
ground loss detection are shown in Section 8.1.5: GND loss detection .
5.8
Charge pump
To effectively bias the high side solenoid drivers and fail safe switch, a charge pump is used to drive the gate
voltage above VBATP. The device uses a common charge pump for all channels and is referred to the battery
voltage supply connected to the VBATP pin. The charge pump output voltage is present at the VCP pin. The
charge pump switching frequency is nominally 470 kHz and its internal control loop reduces emissions by pulse
skipping once the targeted operating voltage is reached.
The charge pump circuit requires three external capacitors. A “Tank” capacitor with a recommended value of 220
nF must be connected between the VCP pin and the VBATP pin. Two pump capacitors with recommended values
of 68 nF must be connected between the VCP1 and VCP2 pins and also between the VCP3 and VCP4 pins. A
built-in monitoring circuit checks if the charge pump output voltage is sufficient to control the high side valve
driver. Additional details for charge pump voltage monitoring are shown in Section 8.1.3: VCP supply under
voltage.
The charge pump voltage is also used as parallel supply to the VDD supply for internal references to avoid ASIC
reset at low VDD input.
L9305
Power supply
DS12774 - Rev 10
page 15/107



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