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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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L9305 датащи(PDF) 51 Page - STMicroelectronics |
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L9305 датащи(HTML) 51 Page - STMicroelectronics |
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51 / 107 page  9.6 SPI electrical specification 4.75 V ≤ VDD ≤ 5.5 V; 5.5 V ≤ VBATP ≤ 19 V; -40 °C ≤ Tj ≤ 175 °C unless otherwise noted. All voltages refer to GNDA pin. Table 38. SPI electrical parameters Symbol Parameter Test condition Min Typ Max Unit Pin SPI_in_low Logic input low detection – – – 0.75 V CS, MOSI, SCLK SPI_in_high Logic input high detection – 1.75 – – V CS, MOSI, SCLK SPI_in_hyst Input hysteresis voltage – 0.1 – – V CS, MOSI, SCLK SPI_in_pd Internal pull down resistance VIN < 2.5 V 20 40 80 kΩ MOSI, SCLK SPI_in_pu Internal pull up resistance VIN < 2.5 V 40 90 180 kΩ CS MISO_Ileak Leakage current in tri-state condition – – – 10 µA MISO MISO_low Logic low level Isink = 1 mA – – 0.4 V MISO MISO_high Logic high level Isource = 1 mA VDDIO-0.4 – – V MISO MISO_trise MISO rise time Cload = 200 pF – – 50 ns MISO MISO_tfall MISO fall time Cload = 200 pF – – 50 ns MISO fclk Transfer Frequency Design info 50% duty cycle, not tested(1) – – 8 MHz SCLK, MOSI, MISO tpcld+tsdo_trans Propagation delay SCLK to data at SDO is valid Cload_max = 200 pF inlcuding parasitics – – 100 ns SCLK, MISO tcsdv NCS=LOW to data at SDO active Cload_max = 200 pF inlcuding parasitics – – 200 ns CS, MISO tpchdz NCS L/H to SDO at high impedance Cload_max = 200 pF inlcuding parasitics – – 200 ns CS, MISO tsclch SCLK before NCS low Design info, not tested 50 – – ns CS, SCLK thclcl SCLK change L/H after NCS=LOW Design info, not tested 130 – – ns CS, SCLK tsclcl SCLK low before NCS high Design info, not tested 50 – – ns CS, SCLK thclch SCLK high after NCS high Design info, not tested 50 – – ns CS, SCLK tscld SDI input setup time Design info, not tested 20 – – ns MOSI thcld SDI input hold time Design info, not tested – – 20 ns MOSI tonNCS NCS min. high time Design info, not tested 650 – – ns CS tclh Minimum Time SCLK=HIGH Design info, not tested 45 – – ns SCLK tcll Minimum Time SCLK=LOW Design info, not tested 45 – – ns SCLK Cin Input pin capacitance Design info, not tested – – 30 pF MOSI, CS, SCLK Cout_hiz MISO output pin capacitance in tri- state Design info, not tested – – 50 pF MISO 1. SPI max frequency may be less depending on the total capacitive load and MCU timing requirements L9305 SPI DS12774 - Rev 10 page 51/107 |
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