L9305 datasheet(11/107 Pages) STMICROELECTRONICS

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Input / Output

4.1

Reset (RESn)

The RESn pin is the reset input for the device. If the RESn pin is low, the device is held in an internal reset state,

all outputs channels are disabled, the failsafe pre-drivers are disabled, the FAULTn pin is held low and all

registers are reset to their default values. An internal pull down current source will hold the RESn pin low in case

the pin is open. RESn pin status is echoed in each SPI frame.

4.2

Enable (EN_DR)

The EN_DR pin is used to enable / disable the output stages. When EN_DR pin is low, all channels are disabled,

all fail safe pre-drivers are disabled and the FAULTn pin is pulled low if EN_DR is not masked. The EN_DR pin

can be connected to a general purpose output pin of the microcontroller or to an alternative safety circuit.

When EN_DR pin is set high, all channels are enabled based on their configuration settings and the fail safe pre-

drivers can be controlled through the Fail Safe Configuration Register.

4.3

Channel inputs (INx/NDISx)

The INx/NDISx pins serve two purposes depending on the selected load control method. If the load is controlled

using the internal closed loop current control circuit (referred to as Hardware Mode), INx/NDISx serves as an

enable/disable signal for each channel. When in this mode, if INx/NDISx is high, output control is disabled and

when low output control is enabled.

The second operating mode is referred to as Software Mode. When the device is programmed for Software Mode,

the INx/NDISx pin serves as the PWM input signal to directly control the output drivers. When INx/NDISx is high,

the driving transistor is enabled and the active recirculation transistor is disabled. When INx/NDISx is low, the

driving transistor is disabled and the active recirculation transistor is enabled. The driving transistor and active

recirculation transistor are dependent on the programmed output configuration, high side or low side. High and

low side configurations are explained in Section 6: Current control drivers.

4.4

Fault (FAULTn)

The device sets the FAULTn pin low upon detecting internal and external faults and while the device is in reset.

The FAULTn pin is open drain and requires an external pull-up resistor connected between VDDIO and the

FAULTn pin. A summary of all faults linked to the state of FAULTn are shown in Table 5 and Table 6. Only faults

with specified masking register bits can be masked or unmasked by the user. Faults denoted as “None” are

automatically linked to FAULTn output status. In addition to the items below, RESn is not masked and is linked to

the FAULTn pin by default.

Table 5. Global and external supply fault pin error masking

FAULTn Masking function

Digital Ground Loss Fault

SERVFLTMSK1, D[15]

Analog Ground Loss Fault

SERVFLTMSK1, D[14]

Fail Safe VDS Fault

SERVFLTMSK1, D[10]

EEPROM Trimming Data CRC Error Fault

SERVFLTMSK1, D[8]

SPI Timeout Latch Fault

SERVFLTMSK1, D[7]

SPI Timeout Fault

SERVFLTMSK1, D[6]

VDD Under Voltage Fault

SERVFLTMSK1, D[4]

VDD Over Voltage Fault

None

V3V3A Over Voltage

None

V3V3D Under Voltage

None

V3V3D Over Voltage

None

Oscillator Stuck

None

Oscillator Mismatch

None

L9305

Input / Output

DS12774 - Rev 10

page 11/107

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