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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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L9305 датащи(PDF) 16 Page - STMicroelectronics |
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L9305 датащи(HTML) 16 Page - STMicroelectronics |
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16 / 107 page  Figure 6. Charge pump mechanization X Charge Pump X X X X X CTANK VC1 VC2 VC3 VC4 VCP C1 C2 VBATP GADG2709181559PS 5.9 Startup & power down sequence L9305 begins initialization and execution of all internal diagnostic and self-test functions upon VDD reaching the VDD_UV threshold. A detailed list of these monitoring functions is summarized in Section 8: Safety features . While the device is initializing, the FAULTn pin remains low. Upon completing initialization, the SPI POR flag is set high (clear on read) to indicate a POR event has occurred and the FAULTn pin remains low until the RESn input is set high. The RESn input can be set high prior to the device completing initialization but the FAULTn pin will not be released until the POR event is complete. This sequence is shown in Figure 7. Also RES_echo in PINSTATUS register is set, when the device exits the reset state in case of Power-On reset event, despite the state of RESn pin. Once the POR event is complete and the RESn input is set high, the device can be configured by the user. All registers maintain RESET default states until both POR is set high and RESn is set by the user. Figure 7. Startup procedure example VDD_UV VCP_UV Internal Operations HiZ VDD RESn FAULTn Case #1: RESn released before internal operations completed VDD_UV VCP_UV Internal Operations VCP VDD RESn FAULTn Case #2: RESn released before internal operations completed HiZ GADG2709181142PS L9305 power down sequence requires only the VDD supply be disabled. Once the VDD_UV threshold is reached, the solenoid and fail safe pre-driver outputs are disabled. There are no timing dependencies between VDD and VBATP voltage levels to perform the power down sequence. L9305 Power supply DS12774 - Rev 10 page 16/107 |
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