TMS320VC33 datasheet(40/53 Pages) TI2

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CLKX/R

FSX(INT)

FSX(EXT)

FSR

Bit 0

Bit n-2

Bit n-3

Bit n-2

Bit n-3

Bit n-1

td(CLKX--FSX)

t d(FSX--DX)V

tsu(FSX--CLKX)

t su(DR--CLKRL)

t d(CLKX--DX)

t h(CLKRL-DR)

th(SCKL-FS)

t su(FSR-CLKRL)

t d(CLKX-DX)V

t dis(CLKX-DXZ)

SM320VC33, SMJ320VC33

SGUS034F – FEBRUARY 2001 – REVISED JUNE 2015

www.ti.com

Timing diagrams show operation with CLKXP = CLKRP = FSXP = FSRP = 0.

Timing diagrams depend on the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively.

The timings that are not specified expressly for the variable data-rate mode are the same as those that are specified

for the fixed data-rate mode.

Figure 35. Variable Data-Rate Mode Timing

8.2.20 HOLD Timing

HOLD is a synchronous input that can be asserted at any time during a clock cycle. If the specified timings are

met, the exact sequence shown in Figure 17 and Figure 18 occurs; otherwise, an additional delay of one clock

cycle is possible.

Timing Requirements for HOLD/HOLDA defines the timing parameters for the HOLD and HOLDA signals.

The NOHOLD bit of the primary-bus control register overrides the HOLD signal. When this bit is set, the device

comes out of hold and prevents future hold cycles.

Asserting HOLD prevents the processor from accessing the primary bus. Program execution continues until a

read from or a write to the primary bus is requested. In certain circumstances, the first write is pending, thus

allowing the processor to continue (internally) until a second external write is encountered.

Figure 17, Figure 18, and the accompanying timings are for a zero wait-state bus configuration. Because HOLD

is internally captured by the CPU on the H1 falling edge one cycle before the present cycle is terminated, the

minimum HOLD width for any bus configuration is, therefore, WTCNT + 3. Also, do not deassert HOLD before

HOLDA has been active for at least one cycle.

8.2.21 General-Purpose I/O Timing

Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. The contents of the internal

control registers associated with each peripheral define the modes for these pins.

8.2.22 Peripheral Pin I/O Timing

Timing Requirements for Peripheral Pin General-Purpose I/O shows the timing parameters for changing the

peripheral pin from a general-purpose output pin to a general-purpose input pin and vice versa.

8.2.23 Timer Pin Timing

Valid logic-level periods and polarity are specified by the contents of the internal control registers.

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