TMS320VC33 datasheet(38/53 Pages) TI2

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100 Ω

TL7705A

RESIN

270 Ω

JP2

180 Ω

TCK_RET (Pin 9)(1)

EMU1 (Pin 14)

EMU0 (Pin 13)

74AS1034

GND (Pins 4,6,8,10,12)

TRST (Pin 2)

TCK (Pin 11)(1)

10.368 MHz

33 Ω

TDI (Pin 3)

TMS (Pin 1)

TDO (Pin 7)

74LVT240

180 Ω

JP1

270 Ω

74F175

+5 V

74AS1004

PD(V

) (Pin 5)

SM320VC33, SMJ320VC33

SGUS034F – FEBRUARY 2001 – REVISED JUNE 2015

www.ti.com

•

A 10.368-MHz test clock source is provided. Another test clock can be used for greater flexibility.

The emulator pod uses TCK_RET as its clock source for internal synchronization. TCK is provided as an

optional target system test clock source.

Figure 33. JTAG Emulator Cable Pod Interface

8.2.16 Reset Timing

RESET is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings

are met, the exact sequence shown in Figure 14 occurs; otherwise, an additional delay of one clock cycle is

possible.

The asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1.

Resetting the device initializes the bus control register to seven software wait states and therefore results in slow

external accesses until these registers are initialized.

HOLD is a synchronous input that can be asserted during reset. It can take nine CPU cycles before HOLDA is

granted.

Timing Requirements for RESET defines the timing parameters for the RESET signal.

8.2.17 Interrupt Response TIming

The interrupt (INTx) pins are synchronized inputs that can be asserted at any time during a clock cycle. The

TMS320C3x interrupts are selectable as level- or edge-sensitive. Interrupts are detected on the falling edge of

H1. Therefore, interrupts must be set up and held to the falling edge of the internal H1 for proper detection. The

CPU and DMA respond to detected interrupts on instruction-fetch boundaries only.

For the processor to recognize only one interrupt when level mode is selected, an interrupt pulse must be set up

and held such that a logic-low condition occurs for:

•

A minimum of one H1 falling edge

•

No more than two H1 falling edges

•

Interrupt sources whose edges cannot be specified to meet the H1 falling edge setup and hold times must be

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