TMS320VC33 datasheet(16/53 Pages) TI2

16 / 53 page

SM320VC33, SMJ320VC33

SGUS034F – FEBRUARY 2001 – REVISED JUNE 2015

www.ti.com

6.28 Switching Characteristics for Serial Port

over recommended operating conditions (see Figure 34 and Figure 35)

PARAMETER

MIN

MAX

UNIT

td(H1H-SCK)

Delay time, H1 high to internal CLKX/R

4(1)

td(CLKX-DX)

Delay time, CLKX to DX valid

CLKX ext

CLKX int

5(1)

td(CLKX-FSX)

Delay time, CLKX to internal FSX high/low

CLKX ext

CLKX int

4(1)

td(CLKX-DX)V

Delay time, CLKX to first DX bit, FSX precedes CLKX high

CLKX ext

CLKX int

5(1)

td(FSX-DX)V

Delay time, FSX to first DX bit, CLKX precedes FSX

tdis(CLKX-DXZ)

Disable time, DX high impedance following last data bit from CLKX high

(1)

Not production tested

6.29 Switching Characteristics for HOLD/HOLDA

over recommended operating conditions for HOLD/HOLDA (see Figure 17 and Figure 18)

PARAMETER

MIN

MAX

UNIT

tv(H1L-HOLDA)

Valid time, HOLDA after H1 low

–1(1)

3(1)

tw(HOLDA)

Pulse duration, HOLDA low

2tc(H) – 4

(1)

td(H1L-SH)H

Delay time, H1 low to STRB high for a HOLD

–1

tdis(H1L-S)

Disable time, STRB to the high-impedance state from H1 low

ten(H1L-S)

Enable time, STRB enabled (active) from H1 low

tdis(H1L-RW)

Disable time, R/W to the high-impedance state from H1 low

5(1)

ten(H1L-RW)

Enable time, R/W enabled (active) from H1 low

tdis(H1L-A)

Disable time, address to the high-impedance state from H1 low

4(1)

ten(H1L-A)

Enable time, address enabled (valid) from H1 low

tdis(H1H-D)

Disable time, data to the high-impedance state from H1 high

4(1)

(1)

Not production tested.

6.30 Switching Characteristics for Peripheral Pin General-Purpose I/O

over recommended operating conditions for peripheral pin general-purpose I/O (see Figure 19 and Figure 20)

(1)

PARAMETER

MIN

MAX

UNIT

td(H1H-GPIO)

Delay time, H1 high to general-purpose output

tdis(H1H)

Disable time, general-purpose output from H1 high

(1)

Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. The modes of these pins are defined by the contents of

internal-control registers associated with each peripheral.

6.31 Switching Characteristics for Timer Pin

over recommended operating conditions for timer pin (see Figure 21 and Figure 22)

PARAMETER

MIN

MAX

UNIT

td(H1H-TCLK)

Delay time, H1 high to TCLK internal valid

tc(TCLK)

(1)

Cycle time, TCLK

TCLK ext

tc(H) × 2.6

(2)

TCLK int

tc(H) × 2

(2)

tc(H) × 232

(2)

tw(TCLK)

(1)

Pulse duration, TCLK

TCLK ext

tc(H) + 5

(2)

TCLK int

[tc(TCLK) / 2] - 4

(2)

[tc(TCLK) / 2] + 4

(2)

(1)

These parameters are applicable for an asynchronous input clock.

(2)

Not production tested

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