TMS320VC33 datasheet(33/53 Pages) TI2

33 / 53 page

CPU Set

IF Bit

RESET

EDGEMODE

CPU Reset

INTn

Delay

D Q

SM320VC33, SMJ320VC33

www.ti.com

SGUS034F – FEBRUARY 2001 – REVISED JUNE 2015

The switch over is synchronous and does not create a clock glitch, so the only effect is that the CPU runs slow

for up to the first 128 cycles after reset goes high. After the PLL has stabilized, the counter remains cleared and

subsequent resets do not exhibit this condition.

Systems that are not using the crystal oscillator may be required to supply a current of 250 mA per DSP if full

power is applied with no clock source. This extra current condition is a result of uninitialized internal logic within

the DSP core and is corrected when the CPU sees a minimum of four internal clocks. The crystal oscillator is

typically immune to this condition since the oscilator and core circuitry become semi-functional at CVDD = 1 V

where the fault current is considerably lower. An alternate clock pulse can also be applied to either the EXTCLK

or XIN clock input pins.

8.2.6 EDGEMODE

When EDGEMODE = 1, a sampled digital delay line is decoded to generate a pulse on the falling edge of the

interrupt pin. To ensure interrupt recognition, input signal logic-high and logic-low states must be held longer than

the synchronizer delay of one CPU clock cycle. Holding these inputs to no less than two cycles in both the logic-

low and logic-high states is sufficient.

When EDGEMODE = 0, a logic-low interrupt pin continually sets the corresponding interrupt flag. The CPU or

DMA can clear this flag within two cycles of it being set. This is the maximum interrupt width that can be applied

if only one interrupt is to be recognized. The CPU can manually clear IF bits within an interrupt service routine

(ISR), effectively lengthening the maximum ISR width.

After reset, EDGEMODE is temporarily disabled, allowing logic-low INT pins to be detected for bootload

operation.

Figure 28. EDGEMODE and Interrupt Flag Circuit

8.2.7 Reset Operation

When RESET is applied, the CPU attempts to safely exit any pending read or write operations that may be in

progress. This can take as much as 10 CPU cycles, after which, the address, data, and control pins are in an

inactive or high-impedance state.

When both RESET and SHZ are applied, the device immediately enters the reset state with the pins held in high-

impedance mode. SHZ should then be disabled at least 10 CPU cycles before RESET is set high. SHZ can be

used during power-up sequencing to prevent undefined address, data, and control pins, avoiding system

conflicts.

8.2.8 PAGE0 to PAGE3 Select Lines

To facilitate simpler and higher-speed connection to external devices, the SMx320VC33 includes four

predecoded select pins that have the same timings as STRB.These pins are decoded from A22, A23, and STRB

and are active only during external accesses over the ranges shown in Table 4. A single bus control register

controls all external bus accesses.

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