TMS320VC33 datasheet(34/53 Pages) TI2

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D Q

Abus

N--Bit

Bank

Compare

Abus_old

N_Wait

Counter

BUS_READY

PAGE_0

PAGE_1

PAGE_2

PAGE_3

Decode

A23

A22

Bus_Enable_Strobe,

0 = Active

Pins

Device

Enable

STRB Pin

READY Pin

R/W Pin

R/ W

0 = Bus Idle

To C31 Style

Decoder

(C31 Compatibility)

SM320VC33, SMJ320VC33

SGUS034F – FEBRUARY 2001 – REVISED JUNE 2015

www.ti.com

Table 4. PAGE0 to PAGE3 Ranges

START

END

PAGE0

0x000000

0x3FFFFF

PAGE1

0x400000

0x7FFFFF

PAGE2

0x800000

0xBFFFFF

PAGE3

0xC00000

0xFFFFFF

8.2.9 Using External Logic With the READY Pin

The key to designing external wait-state logic is the internal bus control register and associated internal logic that

logically combines the external READY pin with the much faster on-chip bus control logic. This essentially allows

slow external logic to interact with the bus while easily meeting the READY input timings. Note that the combined

ready signals are sampled on the rising edge of the internal H1 clock. Refer to Figure 29 for the following

examples.

Example 1: A simple 0 or WTCNT wait-state decoder can be created by simply tying an address line back to the

READY pin and selecting the AND option. When the tied back address is low, the bus runs with 0 wait states.

When the tied back address is high, the bus is controlled by the internal wait-state counter.

By enabling the bank compare logic, proper operation is further ensured by inserting a null cycle before a read

on the next bank is performed (writes are not pre-extended). This extra time can also be used by external logic to

affect the feedback path.

Example 2: An N–WTCNT minimum wait-state decoder can also be created by tying back an address line to

READY and logically ORing it with the internal bank compare and wait count signals. When the address pin is

low, bus timing is determined by the internal WTCNT and BNKCMP settings. When the address line is high, the

bus can run no faster than the WTCNT counter and is extended as long as READY is held high.

Figure 29. Internal Ready Logic, Simplified Diagram

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