TMS320VC33 datasheet(30/53 Pages) TI2

30 / 53 page

SM320VC33, SMJ320VC33

SGUS034F – FEBRUARY 2001 – REVISED JUNE 2015

www.ti.com

8.2 Feature Description

8.2.1 JTAG Scan-Based Emulation Logic

The 320VC33 contains a JTAG port for CPU emulation within a chain of any number of other JTAG devices. The

JTAG port on this device does not include a pin-by-pin boundary scan for point-to-point board level test. The

Boundary Scan tap input and output is internally connected with a single dummy register allowing loop back tests

to be performed through that JTAG domain.

The JTAG emulation port of this device also includes two additional pins, EMU0 and EMU1, for global control of

multiple processors conforming to the TI emulation standard. These pins are open collector-type outputs which

are wire ORed and tied high with a pullup. Non-TI emulation devices should not be connected to these pins.

The VC33 instruction register is 8 bits long. Table 1 shows the instructions code. The uses of SAMPLE and

HIGHZ opcodes, though defined, have no meaning for the SMx320VC33, which has no boundary scan. For

example, HIGHZ affects only the dummy cell (no meaning) and does not put the device pins in a high-impedance

state.

Table 1. Boundary-Scan Instruction Code

INSTRUCTION NAME

INSTRUCTION CODE

EXTEST

00000000

BYPASS

11111111

SAMPLE

00000010(1)

HIGHZ

00000110(1)

PRIVATE1(2)

00000011

PRIVATE2(2)

00100000

PRIVATE3(2)

00100001

PRIVATE4(2)

00100010

PRIVATE5(2)

00100011

PRIVATE6(2)

00100100

PRIVATE7(2)

00100101

PRIVATE8(2)

00100110

PRIVATE9(2)

00100111

PRIVATE10(2)

00101000

PRIVATE11(2)

00101001

(1)

Boundary is only one dummy cell.

(2)

Use of private opcodes could cause the device to operate in an

unexpected manner.

8.2.2 Clock Generator

The clock generator provides clocks to the VC33 device and consists of an internal oscillator and a PLL circuit.

The clock generator requires a reference clock input, which can be provided by using a crystal resonator with the

internal oscillator, or from an external clock source. The PLL circuit generates the device clock by multiplying the

reference clock frequency by a x5 scale factor, allowing use of a clock source with a lower frequency than that of

the CPU. The PLL is an adaptive circuit that, once synchronized, locks onto and tracks an input clock signal.

8.2.3 PLL and Clock Oscillator Control

The clock mode control pins are decoded into four operational modes as shown in Figure 25. These modes

control clock divide ratios, oscillator, and PLL power (see Table 2).

When an external clock input or crystal is connected, the opposite unused input is simply grounded. An XOR

gate then passes one of the two signal sources to the PLL stage. This allows the direct injection of a clock

reference into EXTCLK, or 1- to 20-MHz crystals and ceramic resonators with the oscillator circuit. The two clock

sources include:

•

A crystal oscillator circuit, where a crystal or ceramic resonator is connected across the XOUT and XIN pins

and EXTCLK is grounded.

•

An external clock input, where an external clock source is directly connected to the EXTCLK pin, and XOUT

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