TMS320VC33 datasheet(31/53 Pages) TI2

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Clock Divider

PLL

Clock and Crystal OSC

CLKMD1

CLKMD0

PLL PWR and Bypass

Oscillator Enable

C31 DIV2 Mode

LOWPOWER

MAXSPEED/

IDLE2

CPU CLOCK

1/2

X1, 1/16, Off

XOR

SEL

PLL

EXTCLK

XIN

XOUT

SM320VC33, SMJ320VC33

www.ti.com

SGUS034F – FEBRUARY 2001 – REVISED JUNE 2015

is left unconnected and XIN is grounded.

When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input

signal. When the PLL is locked, it continues to track and maintain synchronization with the input signal. The PLL

is a simple ×5 reference multiplier with bypass and power control.

The clock divider, under CPU control, reduces the clock reference by 1 (MAXSPEED), 1/16 (LOWPOWER), or

clock stop (IDLE2). Wake-up from the IDLE2 state is accomplished by a RESET or interrupt pin logic-low state.

A divide-by-two TMS320C31 equivalent mode of operation is also provided. In this case, the clock output

reference is further divided by two with clock synchronization being determined by the timing of RESET falling

relative to the present H1/H3 state.

Figure 25. Clock Generation

Table 2. Clock Mode Select Pins

CLKMD0

CLKMD1

FEEDBACK

PLLPWR

RATIO

NOTES

Off

Fully static, very-low power

Off

1/2

Oscillator enabled

Off

Oscillator enabled

2 mA at 60 MHz, 1.8-V PLL power. Oscillator enabled

Typical crystals in the 8- to 30-MHz range have a series resistance of 25

Ω, which increases below 8 MHz. To

maintain proper filtering and phase relationships, Rd and Zout of the oscillator circuit should be 10x to 40x that of

the crystal. TI recommends a series compensation resistor (Rd), shown in Figure 26, when using lower frequency

crystals. The XOUT output, the square wave inverse of XIN, is then filtered by the XOUT output impedance, C1

load capacitor, and Rd (if present). The crystal and C2 input load capacitor then refilters this signal, resulting in a

XIN signal that is 75% to 85% of the oscillator supply voltage.

NOTE

Some ceramic resonators are available in a low-cost, three-pin package that includes C1

and C2 internally. Typically, ceramic resonators do not provide the frequency accuracy of

crystals.

Better PLL stability can be achieved using the optional power supply isolation circuit

shown in Figure 26. A similar filter can be used to isolate the PLLVSS, as shown in

Figure 27. PLLVDD can also be directly connected to CVDD.

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