ADRV9002BBCZ datasheet(25/100 Pages) AD

25 / 100 page

Data Sheet

ADRV9002

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

analog.com

Rev. A | 25 of 100

Table 17. Pin Function Descriptions

Pin No.

Type

Mnemonic

Description

Output

RX2_IDATA_OUT−

In LVDS SSI mode, RX2_IDATA_OUT− is the Rx2 I sample data output on the negative side or the Rx2 I

and Q sample data output on the negative side. In CMOS SSI mode, RX2_IDATA_OUT− is the Rx2 Data

Output 0 or the Rx2 I and Q sample data output. If unused, do not connect RX2_IDATA_OUT−.

Output

RX2_IDATA_OUT+

In LVDS SSI mode, RX2_IDATA_OUT+ is the Rx2 I sample data output positive side of the differential

pair or the Rx2 I and Q sample data output positive side of the differential pair. In CMOS SSI mode,

RX2_IDATA_OUT+ is the Rx2 Data Output 1. If unused, do not connect RX2_IDATA_OUT+.

Output

RX2_DCLK_OUT−

In LVDS SSI mode, RX2_DCLK_OUT− is the Rx2 data clock output negative side. In CMOS SSI mode,

RX2_DCLK_OUT− is not used. If unused, do not connect RX2_DCLK_OUT−.

Output

RX2_DCLK_OUT+

In LVDS SSI mode, RX2_DCLK_OUT+ is the Rx2 data clock output positive side. In CMOS SSI mode,

RX2_DCLK_OUT+ is the Rx2 data clock output. If unused, do not connect RX2_DCLK_OUT+.

Input and

Output

DGPIO_15/TX2_

DCLK_OUT+

Digital GPIO 15. VDIGIO_1P8 supplies 1.8 V to DGPIO_15/TX2_DCLK_OUT+. Alternative function of

DGPIO_15/TX2_DCLK_OUT+ is to provide the positive side of the reference clock output for the Tx2

data port in LVDS SSI mode. If unused, do not connect DGPIO_15/TX2_DCLK_OUT+.

Input and

Output

DGPIO_14/TX2_

DCLK_OUT−

Digital GPIO 14. VDIGIO_1P8 supplies 1.8 V to DGPIO_14/TX2_DCLK_OUT−. The alternative function

of DGPIO_14/TX2_DCLK_OUT− is to provide the negative side of the reference clock output for the Tx2

data port in LVDS SSI mode. If unused, do not connect DGPIO_14/TX2_DCLK_OUT−.

Input

VDIGIO_1P8

1.8 V Supply Input for Data Port Interface (CMOS-SSI and LVDS SSI Mode), SPI Signals, Control Input

and Output Signals, and DGPIO Interface.

Output

VDIG_0P9

1.0 V Internal Supply Node for Digital Circuitry. Bypass VDIG_0P9 with a 4.7 µF capacitor.

Input and

Output

DGPIO_12/TX1_

DCLK_OUT−

Digital GPIO 12. VDIGIO_1P8 supplies 1.8 V to DGPIO_12/TX1_DCLK_OUT−. The alternative function

of DGPIO_12/TX1_DCLK_OUT− is to provide the negative side of the reference clock output for the Tx1

data port in LVDS SSI mode. If unused, do not connect DGPIO_12/TX1_DCLK_OUT−.

M10

Input and

Output

DGPIO_13/TX1_

DCLK_OUT+

Digital GPIO 13. VDIGIO_1P8 supplies 1.8 V to DGPIO_13/TX1_DCLK_OUT+. The alternative function

of DGPIO_13/TX1_DCLK_OUT+ is to provide the positive side of the reference clock output for the Tx1

data port in LVDS SSI mode. If unused, do not connect DGPIO_13/TX1_DCLK_OUT+.

M11

Output

RX1_DCLK_OUT+

In LVDS SSI mode, RX1_DCLK_OUT+ is the Rx1 data clock output positive side. In CMOS SSI mode,

RX1_DCLK_OUT+ is the Rx1 data clock output. If unused, do not connect RX1_DCLK_OUT+.

M12

Output

RX1_DCLK_OUT−

In LVDS SSI mode, RX1_DCLK_OUT− is the Rx1 data clock output negative side. In CMOS SSI mode,

RX1_DCLK_OUT− is not used. If unused, do not connect RX1_DCLK_OUT−.

M13

Output

RX1_IDATA_OUT+

In LVDS SSI mode, RX1_IDATA_OUT+ is the Rx1 I sample data output positive side or the Rx1 I and Q

sample data output positive side. In CMOS SSI mode, RX1_IDATA_OUT+ is the Rx1 Data Output 1.

M14

Output

RX1_IDATA_OUT−

In LVDS SSI mode, RX1_IDATA_OUT− is the Rx1 I sample data output negative side or the Rx1 I and Q

sample data output negative side. In CMOS SSI mode, RX1_IDATA_OUT− is the Rx1 Data Output 0 or

the Rx1 I and Q sample data output.

Output

RX2_STROBE_OUT−

In LVDS SSI mode, RX2_STROBE_OUT− is the Rx2 strobe output negative side. In CMOS SSI mode,

RX2_STROBE_OUT− is not used. If unused, do not connect RX2_STROBE_OUT−.

Output

RX2_STROBE_OUT+

In LVDS SSI mode, RX2_STROBE_OUT+ is the Rx2 strobe output positive side. In CMOS SSI mode,

RX2_STROBE_OUT+ is the Rx2 strobe output. If unused, do not connect RX2_STROBE_OUT+.

Output

RX2_QDATA_OUT−

In LVDS SSI mode, RX2_QDATA_OUT− is the Rx2 Q sample data output positive side. In CMOS SSI

mode, RX2_QDATA_OUT− is the Rx2 Data Output 2. If unused, do not connect RX2_QDATA_OUT−.

Output

RX2_QDATA_OUT+

In LVDS SSI mode, RX2_QDATA_OUT+ is the Rx2 Q sample data output positive side. In CMOS SSI

mode, RX2_QDATA_OUT+ is the Rx2 Data Output 3. If unused, do not connect RX2_QDATA_OUT+.

Input

TX2_DCLK_IN+

In LVDS SSI mode, TX2_DCLK_IN+ is the Tx2 data clock input positive side. In CMOS SSI mode,

TX2_DCLK_IN+ is the Tx2 data clock input. If unused, do not connect TX2_DCLK_IN+.

Input

TX2_DCLK_IN−

In LVDS SSI mode, TX2_DCLK_IN− is the Tx2 data clock input negative side. In CMOS SSI mode,

TX2_DCLK_IN− is not used. If unused, do not connect TX2_DCLK_IN−.

N7, N8, P1, P14

Input

VSSD

Digital Supply Voltage (VSSD).

Input

TX1_DCLK_IN−

In LVDS SSI mode, TX1_DCLK_IN− is the Tx1 data clock input negative side. In CMOS SSI mode,

TX1_DCLK_IN− is not used. If unused, do not connect TX1_DCLK_IN−.

N10

Input

TX1_DCLK_IN+

In LVDS SSI mode, TX1_DCLK_IN+ is the Tx1 data clock input positive side. In CMOS SSI mode,

TX1_DCLK_IN+ is the Tx1data clock input. If unused, do not connect TX1_DCLK_IN+.

N11

Output

RX1_QDATA_OUT+

In LVDS SSI mode, RX1_QDATA_OUT+ is the Rx1 Q sample data output positive side. In CMOS SSI

mode, RX1_QDATA_OUT+ is the Rx1 Data Output 3. If unused, do not connect RX1_QDATA_OUT+.

ADRV9002BBCZ датащи(PDF) 25 Page - Analog Devices

ADRV9002BBCZ датащи(HTML) 25 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

датащи скачать

ссылки URL