ADRV9002BBCZ datasheet(23/100 Pages) AD

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Data Sheet

ADRV9002

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. A | 23 of 100

Table 17. Pin Function Descriptions

Pin No.

Type

Mnemonic

Description

Input

RBIAS

Bias Resistor Connection. RBIAS generates an internal current based on an external 1% resistor.

Connect a 4.99 kΩ resistor between RBIAS and VSSA (analog ground) .

Input and

Outputt

VRFLO1_1P0

1.0 V Internal Supply Node for RF LO1 LO Generation Circuitry. Connect VRFLO1_1P0 together with

VRFVCO1_1P0 and bypass with a 4.7 µF capacitor when the internal LDO regulator operated from the

VRFVCO1_1P3 input is in use. Provide a 1.0 V supply to VRFLO1_1P0 when the internal LDO regulator

operated from VRFVCO1_1P3 is not in use.

A10

Input

VRFVCO1_1P3

1.3 V Internal LDO Input Supply for RF LO1 VCO and LO Generation Circuitry. VRFVCO1_1P3 is

sensitive to supply noise.

A11, A12

Input

EXT_LO1−, EXT_LO1+

Differential External LO Input 2. If EXT_LO1+ and EXT_LO1− are used for the external LO2, the input

frequency must be 2× or higher than the desired carrier frequency. For an LO range from 500 MHz to 1

GHz, a 1× multiplier is available. If unused, connect EXT_LO1+ and EXT_LO1− to VSSA.

B1, C1

Input

RX2A−, RX2A+

Differential Input A for Rx2. If unused, connect RX2A− and RX2A+ to VSSA.

Output

VRFVCO2_1P0

1.0 V Internal Supply Node for RF LO2 VCO Circuitry. Connect this VRFVCO2_1P0 together with

VRFLO2_1P0 and bypass with a 4.7 µF capacitor when the internal LDO regulator operated from the

VRFVCO2_1P3 input is in use.

Input

AUXADC_2

Input 2 to Auxiliary ADC Input Multiplexer. If unused, do not connect AUXADC_2.

Input

AUXADC_1

Input 1 to Auxiliary ADC Input Multiplexer. If unused, do not connect AUXADC_1.

Output

VRFVCO1_1P0

1.0 V Internal Supply node for RF LO1 VCO Circuitry. Connect VRFVCO1_1P0 together with

VRFLO1_1P0 and bypass with a 4.7 µF capacitor when the internal LDO regulator operated from

the VRFVCO1_1P3 input is in use.

B14, C14

Input

RX1A−, RX1A+

Differential Input A for Rx1. If unused, connect RX1A− and RX1A+ to VSSA.

C3, C4

Input

RX2B+, RX2B−

Differential Input B for Rx2. If unused, connect RX2B+ and RX2B− to VSSA.

Input and

Output

VANA2_1P0

1.0 V Internal Supply Node for Tx2 and Rx2 Baseband Circuits, TIA, Transmitter Transconductance (GM)

Baseband Filters, and Auxiliary DACs and ADCs. For normal operation, leave VANA2_1P0 unconnected.

Input

VANA2_1P3

1.3 V Internal LDO Input Supply for Tx2 and Rx2 Baseband Circuits, TIA, Transmitter GM, Baseband

Filters, and Auxiliary DACs and ADCs. VANA2_1P3 is sensitive to supply noise.

Input

VANA1_1P3

1.3 V Internal LDO Input Supply for Tx1 and Rx1 Baseband Circuits, TIA, Transmitter GM and Baseband

Filters. VANA1_1P3 is sensitive to supply noise.

Input and

Output

VANA1_1P0

1.0 V Internal Supply Node for Tx1 and Rx1 Baseband Circuits, TIA, Transmitter GM and Baseband

Filters. For normal operation, leave VANA1_1P0 unconnected.

C11, C12

Input

RX1B−, RX1B+

Differential Input B for Rx1. If unused, connect RX1B− and RX1B+ to VSSA.

D7, D8

Input

MCS+, MCS−

Multichip Synchronization Reference Inputs. If unused, connect MCS+ and MCS− to VSSA.

Output

VRX2LO_1P0

1.0 V Internal Supply Node for Rx2 LO Buffers and Mixers. VRX2LO_1P0 is sensitive to supply noise.

Bypass VRX2LO_1P0 with a 4.7 µF capacitor.

Input

VRX2LO_1P3

1.3 V Internal LDO Input Supply for Rx2 LO Buffers and Mixers. Provide a 1.0 V supply to VRX2LO_1P3

when the internal LDO regulator is not used. VRX2LO_1P3 is sensitive to supply noise.

E3, E12, F4, F5, F10, F11, G4,

G6, G9, G11, H6, H9

Input and

Output

AGPIO_xx

GPIOs Signals Referenced to VAGPIO_1P8 1.8 V Supply. See Table 18 to match the ball location to the

AGPIO_xx signal name. Some AGPIO_xx pins can also function as auxiliary DAC outputs. See Table 18

for mapping between AGPIO_xx and the auxiliary DAC signals. If unused, do not connect AGPIO_xx.

Input

VRFSYN2_1P3

1.3 V Supply for RF LO2 Synthesizer. VRFSYN2_1P3 is sensitive to supply noise.

Input

VCLKSYN_1P3

1.3 V Supply for Clock Synthesizer. VCLKSYN_1P3 is sensitive to supply noise.

E7, E8

Input

DEV_CLK_IN+,

DEV_CLK_IN−

Device Clock Input. DEV_CLK_IN± can operate as differential, single-ended, or be connected to the

external crystal oscillator. In single-ended mode, apply the clock signal to the DEV_CLK_IN+ pin and

leave the DEV_CLK_IN− pin unconnected.

E10

Input

VAUXSYN_1P3

1.3 V Supply for Auxiliary Synthesizer. VAUXSYN_1P3 is sensitive to supply noise.

E11

Input

VRFSYN1_1P3

1.3 V Supply for RF LO1 Synthesizer. VRFSYN1_1P3 is sensitive to supply noise.

E13

Input

VRX1LO_1P3

1.3 V Internal LDO Input Supply for Rx1 LO Buffers and Mixers. Provide a 1.0 V supply to VRX1LO_1P3

when the internal LDO regulator is not used. VRX1LO_1P3 is sensitive to supply noise.

E14

Output

VRX1LO_1P0

1.0 V Internal Supply Node for Rx1 LO Buffers and Mixers. VRX1LO_1P0 is sensitive to supply noise.

Bypass VRX1LO_1P0 with a 4.7 µF capacitor.

G1, H1

Output

TX2+, TX2−

Differential Output for Transmitter Channel 2. If unused, do not connect TX2+ and TX2−.

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