ADRV9002BBCZ datasheet(95/100 Pages) AD

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Data Sheet

ADRV9002

THEORY OF OPERATION

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Rev. A | 95 of 100

Figure 362. RF LO

The ADRV9002 supports various forms of fast frequency hopping

(FFH) with the frequency dwell time and transition time as the main

distinguishing factors between these forms. The RF PLL phase

noise and the QEC and LOL algorithm performance degrade as

a function of decreasing frequency transition times. FFH mode sup-

ports hop frequencies that are preloaded at power-up or streamed

by the user onto the ADRV9002. Hopping between the frequencies

in FFH mode can be triggered by toggling a GPIO pin or executing

an API command.

Baseband PLL

The ADRV9002 contains a baseband PLL synthesizer that gen-

erates all baseband and data port related clocks. Two options

are provided for a high performance baseband PLL and a low

power baseband PLL. A high performance baseband PLL offers

greater flexibility in generating clocks to support a wider range

of sample rates. A low power baseband PLL has a limitation in

supporting certain sample rates but consumes less power. Both

high performance and low power baseband PLLs are automatically

programmed based on the data rate and sample rate requirements

of the system.

SPI

The ADRV9002 uses an SPI to communicate with the baseband

processor. This interface can be configured either as a 4-wire

interface with dedicated receive and transmit ports, or as a 3-wire

interface with a bidirectional data communications port. This bus

allows the baseband processor to set all device control parameters

using a simple address data serial bus protocol.

Write commands follow a 24-bit format. The first bit sets the bus

direction of the bus transfer. The next 15 bits set the address where

the data is written. The final eight bits contain the data transferred

to the specific register address. Read commands follow a similar

format with the exception that the first 16 bits are transferred on the

SPI_DIO pin and the final eight bits are read from the ADRV9002

either on the SPI_DO pin in 4-wire mode or on the SPI_DIO pin in

3-wire mode.

GPIO PINS

Digital General-Purpose Inputs/Outputs

(DGPIOs)

The ADRV9002 GPIO signals referenced to the VDIGIO_1P8

supply are intended to interface with digital circuitry and can be

configured for numerous functions. Some of these pins, when

configured as outputs, are used by the baseband processor as

real-time signals to provide a number of internal settings and

measurements. This configuration allows the baseband processor

to monitor receiver performance in different situations. Signals used

for manual gain mode, calibration flags, state machine states, and

various receiver parameters are among the outputs that can be

monitored on these pins. In addition, certain pins can be configured

as inputs and used in various functions, such as setting the receiver

gain or transmitter attenuation in real time.

Analog General-Purpose Inputs/Outputs

(AGPIOs)

The AGPIO pins are intended to interface with system blocks

that perform analog functions. The AGPIO pins referenced to

the VAGPIO_1P8 supply provide control signals to the external

components, such as the low noise amplifier (LNA) or digital step

attenuator (DSA). The selected AGPIO pins provide an alternate

auxiliary DAC functionality. See Table 18 for more details on pin

mapping.

AUXILIARY CONVERTERS

Auxiliary ADC Inputs (AUXADC_x)

The ADRV9002 contains four auxiliary ADCs with the correspond-

ing inputs connected to four dedicated input pins (AUXADC_x).

This block can monitor system voltages without additional compo-

nents. The auxiliary ADC is 10 bits with an input voltage range of

0.05 V to 0.95 V. When enabled, the auxiliary ADC is free running.

An API function allows the user to read back the last value latched

by the ADC.

Auxiliary DACs Outputs (AUXDAC_x)

The ADRV9002 contains four identical auxiliary DACs (AUXDAC_x)

that can supply bias voltages, analog control voltages, or other sys-

tem functionality. The auxiliary DACs (AUXDAC_0 to AUXDAC_3)

are multiplexed with the AGPIO_xx pins, as shown in Table 18. The

auxiliary DACs are 12 bits and have an output voltage range of

approximately 0.05 V to VDDA_1P8 − 0.05 V and have a current

drive of 10 mA. The auxiliary DACs generate ramp up and ramp

down patterns that can be loaded into the ADRV9002 and then

triggered based on state of dedicated DGPIO pin.

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