ADRV9002BBCZ datasheet(16/100 Pages) AD

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Data Sheet

ADRV9002

SPECIFICATIONS

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Rev. A | 16 of 100

Table 5.

Parameter

Min

Typ

Max

Unit

VDDA_1P33 Analog Supplies

1.267

1.3

1.33

VDDA_1P8 Analog Supplies

1.71

1.8

1.89

VDD_1P84 Digital Supply

1.71

1.8

1.89

1 VDDA_1P0 refers to all analog 1.0 V supplies that operate with the internal low dropout (LDO) regulator bypassed. The power domain that allows the internal LDO regulator

bypass includes VRFLO2_1P0, VRFLO1_1P0, VRX2LO_1P3, VRX1LO_1P3, VTX2LO_1P3, VCONV_1P3, and VTX1LO_1P3.

2 VDD_1P0 refers to all digital 1.0 V supplies including VDIG_1P0.

3 VDDA_1P3 refers to all analog 1.3 V supplies including VRFVCO2_1P3, VRFVCO1_1P3, VANA2_1P3, VANA1_1P3, VRX2LO_1P3, VCLKSYN_1P3, VRFSYN2_1P3,

VRFSYN1_1P3, VAUXSYN_1P3, VRX1LO_1P3, VTX2LO_1P3, VCLKVCO_1P3, VAUXVCO_1P3, VTX1LO_1P3, and VCONV_1P3.

4 VDD_1P8 refers to all digital 1.8 V supplies including VDIGIO_1P8.

CURRENT CONSUMPTION ESTIMATES (TYPICAL VALUES)

No external VDDA_1P0 1.0 V power domain is used in Table 6 to Table 11. In all following modes described, the ADRV9002 operates with

internal LDO regulators used to produce an on-chip, 1.0 V analog power domain.

Sleep Mode

Table 6. Digital Mobile Radio (DMR) CMOS SSI

ADRV9002 Mode Conditions

Supply (mA)

Total Average

Power (W)

VDDA_1P0

Analog

Supplies

VDD_1P0

Digital

Supply

VDDA_1P3

Analog

Supplies

VDDA_1P8

Analog

Supplies

VDD_1P8

Digital

Supply

Receiver, Transmitter, Clock PLL, and LDO Regulator Powered

Down, Internal Microprocessor Active, CMOS SSI Interface Off,

DEV_CLK_OUT Off, and Auxiliary DACs Off

Not used

18.9

8.2

9.7

1.3

0.049

Receiver, Transmitter, Clock PLL, LDO Regulator, and Internal

Microprocessor Powered Down, CMOS SSI Interface Off,

DEV_CLK_OUT Off, and Auxiliary DACs Off

Not used

2.3

6.9

9.7

1.3

0.031

Table 7. Long-Term Evolution (LTE) Dual Transmitter and Dual Receiver LVDS SSI

ADRV9002 Mode Conditions

Supply (mA)

Total Average

Power (W)

VDDA_1P0

Analog

Supplies

VDD_1P0

Digital

Supply

VDDA_1P3

Analog

Supplies

VDDA_1P8

Analog

Supplies

VDD_1P8

Digital

Supply

Receiver, Transmitter, Clock PLL, and LDO Regulator Powered Down,

Internal Microprocessor Active, LVDS SSI Interface Off, DEV_CLK_OUT

Off, and Auxiliary DACs Off

Not used

24.6

12.4

11.3

1.3

0.066

Receiver, Transmitter, Clock PLL, LDO Regulator, and Internal

Microprocessor Powered Down, LVDS SSI Interface Off, DEV_CLK_OUT

Off, and Auxiliary DACs Off

Not used

2.3

10.3

10.6

1.3

0.037

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