ADRV9002BBCZ datasheet(19/100 Pages) AD

19 / 100 page

Data Sheet

ADRV9002

SPECIFICATIONS

analog.com

Rev. A | 19 of 100

Table 12.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

tHC

Last SPI_CLK falling edge to SPI_EN hold

SPI_DIO data input setup to SPI_CLK

SPI_DIO data input hold to SPI_CLK

tCO

SPI_CLK falling edge to output data delay (3-wire mode)

SPI_CLK falling edge to output data delay (4-wire mode)

tHZM

tCO

Bus turnaround time after the baseband processor drives the

last address bit

tHZS

tCO

Bus turnaround time after the ADRV9002 drives the last

address bit, not shown in Figure 2

DIGITAL TIMING1

TX1_ENABLE or TX2_ENABLE Pulse Width

µs

RX1_ENABLE or RX2_ENABLE Pulse Width

µs

TX1_ENABLE or TX2_ENABLE Valid Data

µs

RX1_ENABLE or RX2_ENABLE Valid Data

µs

DIGITAL DATA TIMING (LVDS SSI)

Zero on-chip lane skew and an adjustable delay of ±300 ps

available per lane

TXx_DCLK_IN±, RXx_DCLK_OUT± and

TXx_DCLK_OUT± Clock Period

500 MHz

TXx_DCLK_IN±, RXx_DCLK_OUT± and

TXx_DCLK_OUT± Pulse Width

Transmitter Data

TXx_IDATA_IN± or TXx_QDATA_IN or

TXx_STROBE_IN± Setup to TXx_DCLK_IN±

0.22

TXx_IDATA_IN± or TXx_QDATA_IN± or

TXx_STROBE_IN± Hold to TXx_DCLK_IN±

0.39

Receiver Data

RXx_DCLK_OUT± to RXx_IDATA_OUT± or

RXx_QDATA_OUT± or RXx_STROBE_OUT± Delay

0.2

DC-coupled

DIGITAL DATA TIMING (CMOS-SSI)

TXx_DCLK_IN±, RXx_DCLK_OUT± and

TXx_DCLK_OUT± Clock Period

12.5

80 MHz

TXx_DCLK_IN±, RXx_DCLK_OUT± and

TXx_DCLK_OUT± Pulse Width

6.25

Transmitter Data

TXx_DATA_IN± or TXx_STROBE_IN± Setup to

TXx_DCLK_IN±

TXx_DATA_IN± or TXx_STROBE_IN± Hold to

TXx_DCLK_IN±

Receiver Data

RXx_DCLK_OUT± to RXx_DATA_OUT± or

RXx_STROBE_OUT± Delay

4.5

DC-coupled

MULTICHIP SYNCHRONIZATION (MCS) TIMING

LVDS Setup

0.62

LVDS Hold

CMOS Setup

CMOS Hold

1 TX1_ENABLE, TX2_ENABLE, RX1_ENABLE, and RX2_ENABLE are the channel enabling and disabling signals.

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