 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
ADRV9002BBCZ датащи(PDF) 13 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADRV9002BBCZ датащи(HTML) 13 Page - Analog Devices |
|
|
13 / 100 page  Data Sheet ADRV9002 SPECIFICATIONS analog.com Rev. A | 13 of 100 Table 2. Receivers (Rx1A, Rx1B, Rx2A, and Rx2B) Parameter Symbol Min Typ Max Unit Test Conditions/Comments 5800 MHz 70 dB 1 Note that the input signal power limit does not correspond to 0 dBFS at the digital output because of the nature of the continuous time Σ-Δ ADCs. Unlike the hard clipping characteristic of pipeline ADCs, these converters exhibit a soft overload behavior when the input approaches the maximum level. INTERNAL LO, EXTERNAL LO, AND DEVICE CLOCK Table 3. Parameter Symbol Min Typ Max Unit Test Conditions/Comments LO Frequency Step 2.2 Hz For 38.4 MHz DEV_CLK1, use the equation DEV_CLK/((223 − 15) × 2) to calculate, assuming the LO divider is 2 Reference Spurs −80 dBc LO < 1 GHz, PLL bandwidth = 300 kHz LO WITH HIGH PERFORMANCE MODE Integrated Phase Noise Integrated from 100 Hz to 50 MHz 30 MHz LO 0.008 °rms PLL bandwidth = 300 kHz 470 MHz LO 0.04 °rms PLL bandwidth = 300 kHz 900 MHz LO 0.08 °rms PLL bandwidth = 300 kHz 2400 MHz LO 0.22 °rms PLL bandwidth = 300 kHz 3500 MHz LO 0.27 °rms PLL bandwidth = 300 kHz 5800 MHz LO 0.6 °rms PLL bandwidth = 300 kHz Phase Noise DEV_CLK = 38.4 MHz, typical performance 30 MHz LO See Figure 354 PLL bandwidth = 300 kHz 470 MHz LO See Figure 355 PLL bandwidth = 300 kHz 900 MHz LO See Figure 356 PLL bandwidth = 300 kHz 2400 MHz LO See Figure 357 PLL bandwidth = 300 kHz 3500 MHz LO See Figure 358 PLL bandwidth = 300 kHz 5800 MHz LO See Figure 359 PLL bandwidth = 300 kHz LO PHASE SYNCHRONIZATION Initial Phase Synchronization Accuracy 3 Degrees EXTERNAL LO INPUT Input Frequency Input frequency must be 2× or higher than the desired frequency for the LO frequency (fLO), a 1× multiplier is available for an LO range from 500 MHz to 1 GHz fEXTLO 60 12000 MHz Input Signal Power −6 0 +6 dBm 50 Ω matching at the source Input Signal Differential Phase Balance 20 Degrees Do not exceed 20 degrees to ensure adequate quadrature error correction Input Signal Differential Amplitude Balance 1 dB Input Signal Duty Cycle 2.5 % Input Impedance 100 Ω Differential, see the ADRV9001 system development user guide for more information REFERENCE CLOCK (DEV_CLK_IN SIGNAL) Differential mode Frequency Range 10 1000 MHz |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
