ADRV9002BBCZ datasheet(97/100 Pages) AD

97 / 100 page

Data Sheet

ADRV9002

APPLICATIONS INFORMATION

analog.com

Rev. A | 97 of 100

POWER SUPPLY SEQUENCE

The ADRV9002 requires a specific power-up sequence to avoid

undesired power-up currents. The optimal power-on sequence re-

quires VDD_1P0 to power up first. The VDDA_1P3 and VDDA_1P8

supplies must then power up after the VDD_1P0 supply. If

VDDA_1P0 is used, VDDA_1P0 must be powered up after

VDDA_1P3 and VDDA_1P8 are enabled.

The user must toggle the RESET signal after power has stabilized

prior to configuration.

DIGITAL DATA INTERFACE

The ADRV9002 data interface supports both CMOS and LVDS

electrical interfaces. The CSSI is intended for narrow RF signal

bandwidths, and the LVDS synchronous serial interface (LSSI) can

support the full RF bandwidth of the ADRV9002. Table 20 provides

a high level overview. For more details, refer to the ADRV9001

system development user guide.

All signal lanes support both electrical interfaces, but concurrent

operation of both interfaces is not supported. Additionally, each

receive and transmit channel has a dedicated set of lanes for

transferring information. The receive and transmit channels cannot

be reconfigured to an alternative ball configuration that is different

from how it has been assigned by design.

CSSI

The CSSI supports two modes of operation, 1-lane serialized data

or 4-lane data. In either case, the maximum clock frequency sup-

ported by the CMOS configuration is 80 MHz.

For the CSSI in 1-lane data mode, 16 bits of I data and 16 bits of Q

data (a total of 32 data bits) are serialized on a single lane. Figure

363 shows a graphical overview of the CSSI in 1-lane data mode.

For the CSSI in 4-lane data mode, the I and Q digital data is spread

across four data lanes. The 16 bits of I data and 16 bits of Q

data are split into 8 bits and sent over one of four data lanes. For

example, Lane 0 would have 8 LSB bits of I data, Lane 1 would

have 8 MSB bits of I data, Lane 2 would have 8 LSB bits of Q data,

and Lane 3 would have 8 MSB bits of Q data.

The CSSI in 4-lane data mode supports both a full rate clock and a

double data rate (DDR) clock. The DDR clock mode allows data to

be latched on both the rising and falling edges, which enables twice

the available RF bandwidth, as shown in Figure 364.

CSSI Receive

In the receive CMOS configuration, two additional signal lanes are

required for the strobe and clock signals in addition to the data

lane requirement as described for the CSSI in 1-lane mode and the

CSSI in 4-lane mode, which allows a total of three signal lanes for

the CSSI in 1-lane data mode and six total signal lanes for the CSSI

in 4-lane data mode.

RXx_DCLK_OUT is an output clock signal that synchronizes the

data and strobe output signals. RXx_STROBE_OUT is a strobe

output signal that indicates the first bit of the serial data stream.

The RXx_STROBE_OUT signal can be configured to indicate

the start of the I and Q samples. For a 16-bit data sample, the

RXx_STROBE_OUT signal is high for one clock cycle and low for

31 clock cycles. Alternatively, the RXx_STROBE_OUT signal can

be configured to be high for I data duration and low for Q data dura-

tion. In this case, for a 16-bit data sample, the RXx_STROBE_OUT

signal is high for 16 clock cycles (I data) and low for 16 clock cycles

(Q data).

CSSI Transmit

For the transmit CMOS configuration, three additional signal lanes

are required for the strobe, clock input, and clock output in addition

to the data lane requirement as described for the CSSI in 1-lane

data mode and the CSSI in 4-lane data mode, which allows a total

of four signal lanes for the CSSI in 1-lane data mode and seven

total signal lanes for the CSSI in 4-lane data mode.

TXx_DCLK_IN is an input clock to the ADRV9002 that syn-

chronizes to the data inputs (TXx_DATA_IN) and strobe inputs

(TXx_STROBE_IN). TXx_STROBE_IN is an input signal that in-

dicates the first bit of the serial data sample. Similar to the

receive path, the transmit strobe has two configuration options.

The TXx_DCLK_OUT is an output clock from the ADRV9002

to the external baseband device to generate the TXx_DCLK_IN,

TXx_STROBE_IN, and TXx_DATA_IN signals.

LSSI

The LSSI supports the higher RF channel bandwidths and requires

differential signal pairs. In LSSI mode, there are two data transfer

formats, 1-lane data mode, where both the I and Q data are

serialized on a single differential pair, or 2-lane data mode, where

the I and Q data occupy separate differential pairs. The selection

of either 1-lane data mode or 2-lane data mode depends on the

RF channel bandwidth. To capture the maximum 40 MHz RF

bandwidth of the ADRV9002, select the LSSI in 2-lane data mode.

In either case, the maximum clock frequency supported by the LSSI

configuration is 491.52 MHz and the clock type is DDR. Refer to

Figure 365 for more details.

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