MPC8280 datasheet(175/1386 Pages) FREESCALE

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System Interface Unit (SIU)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

4-3

Figure 4-2 is a block diagram of the system configuration and protection logic.

Figure 4-2. System Configuration and Protection Logic

Many aspects of system configuration are controlled by several SIU module configuration registers,

described in Section 4.3.2, “System Configuration and Protection Registers.”

4.1.1

Bus Monitor

The MPC8280 has two bus monitors, one for the 60x bus and one for the local bus. The bus monitor

ensures that each bus cycle is terminated within a reasonable period. The bus monitor does not count when

the bus is idle. When a transaction starts (TS asserted), the bus monitor starts counting down from the

time-out value. For standard bus transactions with an address tenure and a data tenure, the bus monitor

counts until a data beat is acknowledged on the bus. It then reloads the time-out value and resumes the

count down. This process continues until the whole data tenure is completed. Following the data tenure

the bus monitor will idle in case there is no pending transaction; otherwise it will reload the time-out value

and resume counting.

For address-only transactions, the bus monitor counts until AACK is asserted. If the monitor times out for

a standard bus transaction, transfer error acknowledge (TEA) is asserted. If the monitor times out for an

address-only transaction, the bus monitor asserts AACK and a core machine check or reset interrupt is

generated, depending on SYPCR[SWRI]. To allow variation in system peripheral response times,

SYPCR[BMT] defines the time-out period, whose maximum value can be 2,040 system bus clocks. The

timing mechanism is clocked by the system bus clock divided by eight.

4.1.2

Timers Clock

The two SIU timers (the time counter and the periodic interrupt timer) use the same clock source,

timersclk, which can be derived from several sources, as described in Figure 4-3.

Module

Configuration

Bus

Monitors

Periodic Interrupt

Timer

Software

Watchdog Timer

Time

Counter

TEA

Interrupt

Core’s MCP

Interrupt

Core’s MCP

System Reset

timersclk

Bus Clock

timersclk

System Reset

Bus clock/8

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